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Design of NoC Router Architecture using VHDL

by Minakshi M. Wanjari, Pankaj Agrawal, R. V. Kshirsagar
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 115 - Number 4
Year of Publication: 2015
Authors: Minakshi M. Wanjari, Pankaj Agrawal, R. V. Kshirsagar
10.5120/20139-2238

Minakshi M. Wanjari, Pankaj Agrawal, R. V. Kshirsagar . Design of NoC Router Architecture using VHDL. International Journal of Computer Applications. 115, 4 ( April 2015), 18-21. DOI=10.5120/20139-2238

@article{ 10.5120/20139-2238,
author = { Minakshi M. Wanjari, Pankaj Agrawal, R. V. Kshirsagar },
title = { Design of NoC Router Architecture using VHDL },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 115 },
number = { 4 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 18-21 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume115/number4/20139-2238/ },
doi = { 10.5120/20139-2238 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:53:50.934027+05:30
%A Minakshi M. Wanjari
%A Pankaj Agrawal
%A R. V. Kshirsagar
%T Design of NoC Router Architecture using VHDL
%J International Journal of Computer Applications
%@ 0975-8887
%V 115
%N 4
%P 18-21
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Network-on-Chip (NoC) is an advance design method of communication network into System-on-Chip (SoC). It provides solution to the problems of traditional bus-based SoC. It is widely considered that NoC will take the place of traditional bus-based design and will meet the communication requirements of next SoC design. A router is the key component and called as the communication backbone in NoC. This paper presents NoC router architecture which has low latency and requires less area. The design is implemented in VHDL and simulated in Xilinx ISE Design Suite 13. 1.

References
  1. W. J. Dally, "Virtual-channel flow control," IEEE Trans. Parallel Distrib. Syst. , vol. 3, no. 2, Mar. 1992, pp. 194–205.
  2. L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, 2002, pp. 70–78.
  3. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in DAC '01: Proceedings of the 38th Conference on Design Automation, Jun. 2001, pp. 684–689.
  4. P. Guerrier and A. Greiner, "A generic architecture for on-chip packetswitched interconnections," in DATE '00: Proceedings of the Conference on Design, Automation and Test in Europe, Mar. 2000, pp. 250–256.
  5. A. Mello, L. Tedesco, N. Calazans and F. Moraes, "Virtual channels in networks on chip: implementation and evaluation on hermes NoC," in Proceedings of the 18th annual symposium on Integrated circuits and system design, ACM: Florianolpolis, Brazil. 2005.
  6. W. J. Dally, "Virtual-channel flow control," IEEE Trans. Parallel Distrib. Syst. , vol. 3, no. 2, Mar. 1992, pp. 194–205.
  7. J. Suseela and V. Muthukumar, "Loopback Virtual Channel Router Architecture for Network on Chip," in Proceedings of the Ninth International Conference on Information Technology- New Generations. Apr. 2012, pp. 534 – 539.
  8. J. Kim, "Low-cost router micro architecture for on chip networks," in 42nd Annual IEEE/ACM Int. Symp. Micro architecture (MICRO-42), New York, NY, USA, December 2009, pp. 255–266.
  9. W J. Dally, B. Towels, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers Inc, 2003, pp. 305-324.
  10. J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan and C. R. Das, "A low latency router supporting adaptivity for on-chip interconnects," in Proceedings of the 42nd annual Design Automation Conference, . ACM: New York, USA, 2005.
  11. P Gratz, B. Grot, and S. W. Keckler, "Regional congestion awareness for load balance in networks-on-chip," in IEEE 14th International Symposium on High Performance Computer Architecture, HPCA 2008, pp. 203-214.
  12. T. Bjerregaard, J. Sparso, "A router architecture for connection oriented service guarantees in the MANGO clock less network-on chip," in Proceeding of the conference on Design, Automation and Test in Europe, IEEE Computer Society, 2005, pp. 1226-1231.
  13. É. Cota et al. , Reliability, "Availability and Serviceability of Networks-on-Chip", DOI 10. 1007/978-1-4614-0791-1_2, © Springer Science+Business Media, LLC 2012.
  14. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, and Chita R. Das, "Network-on-Chip Architectures A Holistic Design Exploration",DOI 10. 1007/978-90-481-3031-3, © Springer Science+Business Media B. V. 2009.
  15. Everton Carara, Ney Calazans, Fernando Moraes , " A New Router Architecture for High-Performance Intrachip Networks ," Journal Integrated Circuits and Systems 2008; v. 3 / n. 1:23-31
  16. Moraes, F. ; Calazans, N. ; Mello, A. ; Möller, L. ; Ost, L. "HERMES: an Infrastructure for Low Area Overhead Packetswitching Networks on Chip". Integration the VLSI Journal, 38(1), Oct. 2004, pp. 69-93.
  17. Swapna S. ; Swain, A. K. ; Mahapatra, K. K. , "Design and analysis of five port router for network on chip," Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in, doi: 10. 1109/PrimeAsia. 2012. 6458626 , 5-7 Dec. 2012 pp. 51,55
  18. Mr. Ashish Khodwe, Prof. C. N. Bhoyar, "Efficient FPGA Based Bidirectional Network on Chip Router throgh Virtual Channel Regulator" in International Journal of Advances in Engineering Sciences Vol. 3 (3), July, 2013 e-ISSN: 2231-0347 Print-ISSN: 2231-2013, pp. 82-87.
  19. Brahim Attia, Wissem Chouchene, Abdelkrim Zitouni, Noureddine Abid,and Rached Tourki, A Modular Router Architecture Design For Network on Chip, 978-1-4577-0411-6/11/$26. 00 ©2011 IEEE.
Index Terms

Computer Science
Information Sciences

Keywords

Network-on-Chip (NoC) System-on-Chip (SoC) Processing Element (PE) Network Interface (NI) Virtual Channel (VC).

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