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VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder

by J.eric Clapten, E.konguvel, M.thangamani
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 115 - Number 6
Year of Publication: 2015
Authors: J.eric Clapten, E.konguvel, M.thangamani
10.5120/20153-2298

J.eric Clapten, E.konguvel, M.thangamani . VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder. International Journal of Computer Applications. 115, 6 ( April 2015), 5-8. DOI=10.5120/20153-2298

@article{ 10.5120/20153-2298,
author = { J.eric Clapten, E.konguvel, M.thangamani },
title = { VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 115 },
number = { 6 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 5-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume115/number6/20153-2298/ },
doi = { 10.5120/20153-2298 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:54:01.997527+05:30
%A J.eric Clapten
%A E.konguvel
%A M.thangamani
%T VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 115
%N 6
%P 5-8
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Carry Select Adder (CSLA) is one of the speedest adder utilized as a part of numerous computational frameworks to perform quick number-crunching operations. The Carry select adder utilizes an effective plan by imparting the Common Boolean logic (CLB) term. The modified CSLA architecture building design has created utilizing Binary to Excess-1 converter (BEC). This paper introduces an unique method that replaces the BEC using common Boolean logic. Experimental analysis illustrates that the proposed architecture achieves advantages in terms of speed, area consumption and power.

References
  1. B. Ramkumar and Harish M Kittur, "Low power and area efficient carry select adder", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb 2012.
  2. J. M. Rabaey, Digital Integrated Circuits-A Design Perspective, Upper Saddle River, NJ: Prentice-Hall, 2001.
  3. Shalemraju Kolasani, K. Hanumantha Rao & T. Malyadri," A Novel Designing Approach for high speed carry Select adder", International Journal of Computer Science and Electrical Engineering (IJCSEE) ISSN No. 2315-4209, Vol-1, Iss-2, 2012.
  4. Z. Abid, H. El-Razouk and D. A. El-Dib, "Low power multipliers based on new hybrid full adders", Microelectronics Journal, Volume 39, Issue 12, Pages 1509-1515, 2005.
  5. A. Tyagi, "A reduced area scheme for carryselect adders", IEEE Trans. on Computer, vol. 42, pp. 1163- 1170, 1993.
  6. Hasan Krad and Aws Yousif Al-Taie, "Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL", Journal of Computer Science 4 (4): 305-305, 2005.
  7. B. Ramkumar and Harish M Kittur, "LowPower and Area-Efficient Carry Select Adder", IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 20, no. 2, February 2012.
  8. B. Ramkumar, H. M. Kittur, and P. M. Kannan, ?ASIC implementation of modified faster carry save adder,? Eur. J. Sci. Res. , vol. 42, no. 1, pp. 53–55, 2010.
  9. http://www. ijmra. us/project%20doc/IJMIE_MAY2012/IJMRA-MIE1152. pdf
  10. http://www. ijesit. com/Volume%202/Issue%204/IJESIT201304_49. pdf
  11. http://airccse. org/journal/ijdms/papers/3411ijdms01. pdf
  12. http://www. slideshare. net/ijeraeditor/eq36876880
  13. http://www. academia. edu/10177958/An_Area_Efficient_Carry_Select_Adder_for_Signal_Processing_Applications
  14. http://www. jatit. org/volumes/Vol64No3/18Vol64No3. pdf
  15. J. Raja, M. Kannan, VLSI implementation of high throughput MIMO OFDM transceiver for 4th Generation systems. ,international journal of Engineering and materials sciences,Vol. 19 ,October 2012, pp. 307-312.
  16. E. Konguvel, J. Raja, M. Kannan, A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme, International Journal of Computer Applications (0975 – 8887) Volume 77 – No. 5, September 2013.
  17. A. Amjadha, E. Konguvel, J. Raja, Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation System International Journal of Computer Applications (0975 – 8887) Volume 89 – No 12, March 2014.
  18. Basant Kumar Mohanty and Sujit Kumar Patel, Area–Delay–Power Efficient Carry Select Adder" IEEE Transactions on Circuits and Systems—II: Express briefs, Vol. 61, no. 6,June 2014.
Index Terms

Computer Science
Information Sciences

Keywords

Carry Select Adder Area-Efficient BEC