The week's pick
Reseach Article
A Low Power VLSI Implementation of STTRAM based TCAM for High Speed Switching Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 115 - Number 7 |
| Year of Publication: 2015 |
| Authors: G.karpagam, E.konguvel, M.thangamani |
10.5120/20167-2299
|
G.karpagam, E.konguvel, M.thangamani . A Low Power VLSI Implementation of STTRAM based TCAM for High Speed Switching Circuits. International Journal of Computer Applications. 115, 7 ( April 2015), 38-42. DOI=10.5120/20167-2299
Abstract
Ternary content-addressable memory (TCAM) is often used in high speed search intensive applications such as ATM switch, IP filters. Hence, currently ZTCAM, is introduced which emulates the TCAM functionality with SRAM. It has some drawbacks such as low scalability, low storage density, slow access time and high cost. But this paper proposes novel memory architecture of existing Z-TCAM, but with STTRAM instead of SRAM. Hence the area, delay and power by using lower power consumption Spin Transfer Torque RAM (STT RAM) instead of SRAM. The detailed implementation results and power measurements for each design have been reported thoroughly.
References
- Zahid Ullah, Manish K. Jaiswal, and Ray C. C. Cheung, "Z-TCAM: An SRAM-based Architecture for TCAM," IEEE Transaction on Very Large Scale Integration. (VLSI) Systems,vol. 23,no. 2, pp. 402-406, 2015.
- Philip Asare and Ben Melton, "Towards An Early Design Space Exploration Tool Set for Spin Transfer Torque RAM (STT-RAM) Design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
- P. Mahoney, Y. Savaria, G. Bois, and P. Plante, "Parallel hashing memories: An alternative to content addressable memories," in Proc. 3rd Int. IEEE-NEWCAS Conf. , Jun. 2005, pp. 223–226.
- S. Dharmapurikar, P. Krishnamurthy, and D. Taylor, "Longest prefix matching using bloom filters," IEEE/ACM Trans. Netw. , Apr. 2006.
- D. E. Taylor, "Survey and taxonomy of packet classification techniques," ACM Comput. Surveys, New York, NY, USA: Tech. Rep. WUCSE-2004-24, 2004.
- P. Mahoney, Y. Savaria, G. Bois, and P. Plante, "Transactions on high performance embedded architectures and compilers II," in Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories, P. Stenström, Ed. Berlin, Germany: Springer-Verlag, 2009.
- S. V. Kartalopoulos, "RAM-based associative content-addressable memory device, method of operation thereof and ATM communication switching system employing the same," U. S. Patent 6 097 724, Aug. 1, 2000.
- https://supportforums. cisco. com/document/60831/cam-content-addressable-memory-vs-tcam-ternary-content-addressable-memory
- W. Jiang and V. Prasanna, "Scalable packet classification on FPGA,"IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 20, no. 9, pp. 1668–1680, Sep. 2012.
- M. Becchi and P. Crowley, "Efficient regular expression evaluation: Theory to practice," in Proc. 4th ACM/IEEE Symp. Archit. Netw. Commun. Syst. , Nov. 2008, pp. 50–59.
- Xilinx, San Jose, CA, USA. Xilinx FPGAs [Online].
- W. Jiang and V. K. Prasanna, "Large-scale wire-speed packet classification on FPGAs," in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, 2009, pp. 219–228.
- W. Jiang and V. Prasanna, "Parallel IP lookup using multiple SRAM based pipelines," in Proc. IEEE Int. Symp. Parallel Distrib. Process. , Apr. 2008, pp. 1–14.
- S. Cho, J. Martin, R. Xu, M. Hammoud, and R. Melhem, "CA-RAM: A high-performance memory substrate for search-intensive applications,"in Proc. IEEE Int. Symp. Perform. Anal. Syst. Softw. , Apr. 2007, pp. 230–241.
- M. Somasundaram, "Memory and power efficient mechanism for fast table lookup," U. S. Patent 20 060 253 648, Nov. 2, 2006.
- M. Somasundaram, "Circuits to generate a sequential index for an input number in a pre-defined list of numbers," U. S. Patent 7 155 563, Dec. 26, 2006.
- K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE J. Solid- State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
- Xilinx, San Jose, CA, USA. Xilinx Xpower Analyzer .
- OSUCells, Stillwater, OK, USA [Online]. Available: http://vlsiarch. ecen. okstate. edu
- S. -J. Ruan, C. -Y. Wu, and J. -Y. Hsieh, "Low power design of precomputation-based content-addressable memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 16, no. 3, pp. 331–335, Mar. 2008.
- J. Raja, M. Kannan, VLSI implementation of high throughput MIMO OFDM transceiver for 4th Generation systems. ,international journal of Engineering and materials sciences,Vol. 19 ,October 2012, pp. 307-312.
- E. Konguvel, J. Raja, M. Kannan, A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme, International Journal of Computer Applications (0975 – 8887) Volume 77 – No. 5, September 2013.
- A. Amjadha, E. Konguvel, J. Raja, Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation System. International Journal of Computer Applications (0975 – 8887) Volume 89 – No 12, March 2014.
Index Terms
Keywords