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Area Efficient Design Analysis of Carry Look Ahead Adder

International Journal of Computer Applications
© 2015 by IJCA Journal
Volume 119 - Number 20
Year of Publication: 2015
Anku Bala
Rajesh Mehra

Anku Bala and Rajesh Mehra. Article: Area Efficient Design Analysis of Carry Look Ahead Adder. International Journal of Computer Applications 119(20):1-4, June 2015. Full text available. BibTeX

	author = {Anku Bala and Rajesh Mehra},
	title = {Article: Area Efficient Design Analysis of Carry Look Ahead Adder},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {119},
	number = {20},
	pages = {1-4},
	month = {June},
	note = {Full text available}


This paper provides a low power solution for Very Large Scale Integration. Power consumption of a circuit and its area occupied are major constraints for a VLSI designer. So in this paper we focused mainly on these two parameters by using different design methodologies such as Fully Automatic, Semi-custom and Fully Custom. Addition is basic operation in any system, but it requires more time as the number of bits are increased. So we use carry look ahead adder to reduce the processing time in circuits like processors or any other circuit. Design of CLA adder using semi-custom and fully custom approach can reduce the area and power consumption to a great extent.


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