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Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic

by Priti Gupta, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 119 - Number 6
Year of Publication: 2015
Authors: Priti Gupta, Rajesh Mehra
10.5120/21073-3747

Priti Gupta, Rajesh Mehra . Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic. International Journal of Computer Applications. 119, 6 ( June 2015), 23-26. DOI=10.5120/21073-3747

@article{ 10.5120/21073-3747,
author = { Priti Gupta, Rajesh Mehra },
title = { Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic },
journal = { International Journal of Computer Applications },
issue_date = { June 2015 },
volume = { 119 },
number = { 6 },
month = { June },
year = { 2015 },
issn = { 0975-8887 },
pages = { 23-26 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume119/number6/21073-3747/ },
doi = { 10.5120/21073-3747 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:03:21.024306+05:30
%A Priti Gupta
%A Rajesh Mehra
%T Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 119
%N 6
%P 23-26
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The main issue in designing of VLSI circuits is power consumption and area requirement In this paper Multiplexer circuit is proposed with the help of transmission gate logic using 6 transistors. Different design methodologies are used for designing of multiplexer layout. Multiplexer is essential circuit for different field of network and communication. Multiplexer requires less number of transistors using transmission gate logic. The main concerned of this paper is to reduce area, power consumption and complexity of Multiplexer using different design methodologies.

References
  1. Rekha Pimoli, Rajesh Mehra, " CMOS design and simulation of 4:1 MUX with transmission gate using 90nm Technology", International Journal of Engineering and Advanced Technology (IJEAT)Vol. 3, Issue 3, pp. 21-24, Feb 2014.
  2. Sanjeet Kumar Sinha and Saurabh Chaudhury, "Comparative Analysis of leakage power with 10 nm channel length in MOSFET/CNTFET devices", Journal of Electron Devices , Vol 20, pp. 1718-1723, May 2014.
  3. G. Moore, "Progress in Digital Electronics", IEDM Tech Digest, 11-13 (1975).
  4. Pushpa Saini, Rajesh Mehra, "Leakage Power reduction in CMOS VLSI Circuits", International Journal of Computer Application, Vol. 5, pp. 42-48, Oct 2012.
  5. K. Nehru, A. shanmugam Dr. , G. Darmila thenmozhi, " Design of Low powerALU using 8 T FA and PTL based MUX circuits",IEEE International Conference on advances in Engineering, Science and Management", pp. 145-149, March 2014.
  6. Neil H. E. Waste, Kamran Eshraghian, "Principle of CMOS VLSI design", Pearson Education, Second Edition, pp. 9,413, 417.
  7. Douglas A. Pucknell, Kamran Eshraghian, " Basic VLSI Design", PHI, Third Edition, pp. 2, 113.
  8. Abdhesh Kumar Jha , Anshul Jain"Comparative Analysis of Demultiplexer using Different Logic Styles", International Journal for Scientific Research & Development, Vol. 2, Issue 12, 2015
  9. P. Upadhaya, Rajesh Mehra, "Low Power design of a SRAM cell for Portable Devices", IEEE International Conference on Computer and Communication Technology (ICCCT) , Vol. 10, pp. 255- 259, 2010.
Index Terms

Computer Science
Information Sciences

Keywords

CMOS technology Layout Microwind tool Pass Transistor Transmission gate Transistor