The week's pick
Random Articles
Reseach Article
A Novel VLSI Architecture for Reversible ALU Logic Gate Structure
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 120 - Number 2 |
| Year of Publication: 2015 |
| Authors: Suman Yadav, Manish Saxena |
10.5120/21196-3861
|
Suman Yadav, Manish Saxena . A Novel VLSI Architecture for Reversible ALU Logic Gate Structure. International Journal of Computer Applications. 120, 2 ( June 2015), 1-3. DOI=10.5120/21196-3861
Abstract
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the design reversible ALU based on different types of reversible gate used with minimal delay, and may be configured to produce a variety of logical calculations. The proposed reversible ALU based on DKG gates is verified and its advantages over the only existing adder design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using VHDL test bench.
References
- H. Thapliyal and N. Ranganathan, "Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate," Proc. of the I ComputerSociety Annual Symposium on VLSI, 2009.
- M. Morrison and N. Ranganathan, "Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures," IEEE International Symposium on VLSI, 2011, pp. 126-131.
- M. Haghparast, S. J. Jassbi, K. Navi and O. Hashemipour, "Design of a NovelReversible Multiplier Circuit using HNG Gate in Nanotechnology", WorldApplied Sci. J. , Vol. 3, , 2008, pp. 974-978.
- H. Thapliyal, N. Ranganathan, and R. Ferreira, "Design of a Comparator Tree Based on Reversible Logic," 10th Proceedings of the IEEE International Conference on Nanotechnology, 2010, pp 1113-6.
- P. Gupta, A. Agarwal, and N. K. Jha. An algorithm for synthesis of reversible logic ciruits. IEEE Trans. Computer-Aided Design, 25(11):2317–2330, Nov 2006.
- D. Maslov and G. W. Dueck. Reversible cascades with minimal garbage. IEEE Trans. Computer-Aided Design, 23(11):1497–1509, November 2004.
- M. Nachtigal and N. Ranganathan. Design and analysis of a novel reversible en-coder/decoder. In Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on,pages 1543 –1546, aug. 2011.
- James Donald and Niraj K. Jha. Reversible logic synthesis with fredkin and peres gates. J. Emerg. Technol. Comput. Syst. , 4:2:1–2:19, April 2008.
- Oleg Golubitsky and Dmitri Maslov. A study of optimal 4-bit reversible toffoli circuits and their synthesis. IEEE Transactions on Computers, 99(PrePrints), 2011.
- Oleg Golubitsky, Sean M. Falconer, and Dmitri Maslov. Synthesis of the optimal 4-bit reversible circuits. In Proceedings of the 47th Design Automation Conference, DAC '10, pages 653–656, New York, NY, USA, 2010. ACM.
Index Terms
Keywords