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Reseach Article

Review Paper on Fast DHT Algorithm using Vedic Mathematics

by Shirali Parsai, Swapnil Jain, Jyoti Dangi
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 120 - Number 8
Year of Publication: 2015
Authors: Shirali Parsai, Swapnil Jain, Jyoti Dangi
10.5120/21248-4062

Shirali Parsai, Swapnil Jain, Jyoti Dangi . Review Paper on Fast DHT Algorithm using Vedic Mathematics. International Journal of Computer Applications. 120, 8 ( June 2015), 32-35. DOI=10.5120/21248-4062

@article{ 10.5120/21248-4062,
author = { Shirali Parsai, Swapnil Jain, Jyoti Dangi },
title = { Review Paper on Fast DHT Algorithm using Vedic Mathematics },
journal = { International Journal of Computer Applications },
issue_date = { June 2015 },
volume = { 120 },
number = { 8 },
month = { June },
year = { 2015 },
issn = { 0975-8887 },
pages = { 32-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume120/number8/21248-4062/ },
doi = { 10.5120/21248-4062 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:05:42.337449+05:30
%A Shirali Parsai
%A Swapnil Jain
%A Jyoti Dangi
%T Review Paper on Fast DHT Algorithm using Vedic Mathematics
%J International Journal of Computer Applications
%@ 0975-8887
%V 120
%N 8
%P 32-35
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Discrete Hartley Transform (DHT) is one of the transform used for converting data in time domain into frequency domain using only real values. DHT can be used for highly modular and parallel processing of data in VLSI applications. We have proposed a new algorithm for calculating DHT of length 2N, where N=3 and 4. We have implemented multiplier as an improvement in place of simple multiplication used in conventional DHT. This paper gives a comparison between conventional DHT algorithm and proposed DHT algorithm in terms of delays and area.

References
  1. H. M. de Oliveir a, R. J. de Sobr al Cintr a, R. M. Camp el lo de Souza, "A F A CTORIZA TION SCHEME FOR SOME DISCRETE HAR TLEY TRANSFORM MATRICES", VOL. 60, NO. 5, MAY 2013.
  2. Said Boussakta, Member, IEEE, Osama Hamoud Alshibami, Student Member, IEEE, and Mohammed Yunis Aziz, Student Member, IEEE,"Radix-2 2 2 Algorithm for the 3-D Discrete Hartley Transform", IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 49, NO. 12, DECEMBER 2001.
  3. Gautam Abhaychand Shah, Tejmal Saubhagyamal Rathore, "A Fast Radix-4 Algorithm and Architecture for DHT", Vol-2 No 5 October, 2011.
  4. Doru Florin Chiper, Senior Member, IEEE, "Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II", IEEE SIGNAL PROCESSING LETTERS, VOL. 18, NO. 11, NOVEMBER 2011.
  5. M. N. Murty, "NOVEL RECURSIVE ALGORITHM FOR REALIZATION OF ONE-DIMENSIONAL DISCRETE HARTLEY TRANSFORM", IJRRAS 10 (2) ? February 2012.
  6. Doru Florin Chiper, Senior Member, IEEE, "A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 5, MAY 2013.
  7. Sushma R. Huddar and Sudhir Rao, Kalpana M. , "Novel High Speed Vedic Mathematics Multiplier using Compressors", 978-1 - 4673-5090-7/13/$31. 00 ©2013 IEEE.
  8. S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, "Implementation of Vedic multiplier for Digital Signal Processing", International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Joural of Computer Applications® (IJCA), pp. 1 -6
  9. Himanshu Thapaliyal and M. B Srinivas, "VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics", Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad, India.
  10. Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, "Vedic Mathematics: Sixteen simple Mathematical Formulae from the Veda", Delhi (2011).
Index Terms

Computer Science
Information Sciences

Keywords

Discrete Hartley Transform (DHT Urdhwa Multiplier and Xilinx Vertex family.