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FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

by Ankit Agrawal, Rakesh Bairathi, Amit Joshi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 124 - Number 3
Year of Publication: 2015
Authors: Ankit Agrawal, Rakesh Bairathi, Amit Joshi
10.5120/ijca2015904528

Ankit Agrawal, Rakesh Bairathi, Amit Joshi . FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform. International Journal of Computer Applications. 124, 3 ( August 2015), 23-28. DOI=10.5120/ijca2015904528

@article{ 10.5120/ijca2015904528,
author = { Ankit Agrawal, Rakesh Bairathi, Amit Joshi },
title = { FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform },
journal = { International Journal of Computer Applications },
issue_date = { August 2015 },
volume = { 124 },
number = { 3 },
month = { August },
year = { 2015 },
issn = { 0975-8887 },
pages = { 23-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume124/number3/22084-2015904528/ },
doi = { 10.5120/ijca2015904528 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:13:25.532922+05:30
%A Ankit Agrawal
%A Rakesh Bairathi
%A Amit Joshi
%T FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform
%J International Journal of Computer Applications
%@ 0975-8887
%V 124
%N 3
%P 23-28
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Transformation is one of the fundamental blocks of many signal processing applications. The Hadamard transform is useful in variety of application including  data encryption methods and latest data compression algorithms such as JPEG extended range (JPEG XR), High Efficiency Video Coding (HEVC) etc. Hadamard transform is multiplier less technique and requires additions and subtractions only. In this paper, we have proposed an efficient method of 4 and 8 points Hadamard transformation using a parallel processing to achieve higher speed. The 8-point DHT has been realized with 4 points DHT implementation. The modules are synthesized using Xilinx ISE 14.2 software with the usage of inbuilt memory core generator for storing co-efficient values. The performance has been verified with area and timing analysis. The proposed implementation shows excellent results and also compared to previous works.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Distributed memory Frequency domain Real time implementation Reconfiguarble Synthesize.

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