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Reseach Article

Noise Tolerant Stochastic Logic Gate Circuits Synthesis using Genetic Algorithms

by I. Neri, F. Hartmann
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 125 - Number 1
Year of Publication: 2015
Authors: I. Neri, F. Hartmann

I. Neri, F. Hartmann . Noise Tolerant Stochastic Logic Gate Circuits Synthesis using Genetic Algorithms. International Journal of Computer Applications. 125, 1 ( September 2015), 1-5. DOI=10.5120/ijca2015905651

@article{ 10.5120/ijca2015905651,
author = { I. Neri, F. Hartmann },
title = { Noise Tolerant Stochastic Logic Gate Circuits Synthesis using Genetic Algorithms },
journal = { International Journal of Computer Applications },
issue_date = { September 2015 },
volume = { 125 },
number = { 1 },
month = { September },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-5 },
numpages = {9},
url = { },
doi = { 10.5120/ijca2015905651 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T23:15:01.401052+05:30
%A I. Neri
%A F. Hartmann
%T Noise Tolerant Stochastic Logic Gate Circuits Synthesis using Genetic Algorithms
%J International Journal of Computer Applications
%@ 0975-8887
%V 125
%N 1
%P 1-5
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

In this paper we propose a method for synthesis of combinational networks using non conventional logic gates. The logic components considered are Stochastic Logic Gates (SLGs) able to change their logic functionality by means of a single control parameter and the environmental level of noise. SLGs are able to adapt their computed logic function depending on the environmental conditions. Circuits composed of SLGs are thus sensitive to changes in the environment which alter the computed logic function. We propose a solution for the synthesis of SLGs combinational networks able to produce a network operating fault tolerant in different environmental conditions, i.e. different levels of noise. Given a description of the problem, in form of a truth table, the synthesis of the network is performed by means of genetic algorithms. The proposed solution is tested with a half-adder and compared to the optimal solution found with an exhaustive search.

  1. K Murali, Sudeshna Sinha, William L Ditto, and Adi R Bulsara. Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor. Physical review letters, 102(10):104101, 2009.
  2. F Hartmann, A Forchel, I Neri, L Gammaitoni, and L Worschech. Nanowatt logic stochastic resonance in branched resonant tunneling diodes. Applied Physics Letters, 98(3):032110, 2011.
  3. Kurt Wiesenfeld and Fernan Jaramillo. Minireview of stochastic resonance. Chaos: An Interdisciplinary Journal of Nonlinear Science, 8(3):539–548, 1998.
  4. Luca Gammaitoni, Peter H¨anggi, Peter Jung, and Fabio Marchesoni. Stochastic resonance. Reviews of modern physics, 70(1):223, 1998.
  5. Julian F Miller, Peter Thomson, and Terence Fogarty. Designing electronic circuits using evolutionary algorithms. arithmetic circuits: A case study, 1997.
  6. Carlos A Coello, Alan D Christiansen, and Arturo Hern´andez Aguirre. Automated design of combinational logic circuits using genetic algorithms. In Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms, pages 335–338, 1997.
  7. Ahmed T Soliman and Hazem M Abbas. Combinational circuit design using evolutionary algorithms. In Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on, volume 1, pages 251–254. IEEE, 2003.
  8. CK Vijayakumari, P Mythili, Rekha K James, and CV Anil Kumar. Genetic algorithm based design of combinational logic circuits using universal logic modules. Procedia Computer Science, 46:1246–1253, 2015.
  9. Didier Keymeulen, Adrian Stoica, Ricardo Zebulum, Yili Jin, and Vu Duong. Fault-tolerant approaches based on evolvable hardware and using a reconfigurable electronic devices. In Integrated Reliability Workshop Final Report, 2000 IEEE International, pages 32–39. IEEE, 2000.
  10. P Nirmal Kumar, S Anandhi, and J Perinbam. Evolving virtual reconfigurable circuit for a fault tolerant system. In Evolutionary Computation, 2007. CEC 2007. IEEE Congress on, pages 1555–1561. IEEE, 2007.
  11. Kyung-Joong Kim and Sung-Bae Cho. Automated synthesis of multiple analog circuits using evolutionary computation for redundancy-based fault-tolerance. Applied Soft Computing, 12(4):1309–1321, 2012.
  12. Hui-CongWu. Fault tolerant circuit design using evolutionary algorithms. Journal of Computers, 9(1):95–100, 2014.
  13. P. Pfeffer, F. Hartmann, S. H¨ofling, M. Kamp, and L. Worschech. Logical stochastic resonance with a coulombcoupled quantum-dot rectifier. Phys. Rev. Applied, 4:014011, Jul 2015.
  14. M. Karnaugh. The map method for synthesis of combinational logic circuits. American Institute of Electrical Engineers, Part I: Communication and Electronics, Transactions of the, 72(5):593–599, Nov 1953.
  15. Thomas B¨ack. Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms. Oxford university press, 1996.
  16. Kit-Sang Tang, Kim-Fung Man, Sam Kwong, and Qun He. Genetic algorithms and their applications. Signal Processing Magazine, IEEE, 13(6):22–37, 1996.
  17. Pinaki Mazumder and Elizabeth M Rudnick. Genetic algorithms for VLSI design, layout & test automation. Prentice Hall PTR, 1999.
  18. David E Golberg. Genetic algorithms in search, optimization, and machine learning. Addion wesley, 1989, 1989.
Index Terms

Computer Science
Information Sciences


Stochastic Logic Gate Fault Tolerant Genetic Algorithm Non Conventional Computing