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Reseach Article

Ber Analysis of Turbo Code Interleaver

by Prabhavati D. Bahirgonde, Shantanu K. Dixit
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 126 - Number 14
Year of Publication: 2015
Authors: Prabhavati D. Bahirgonde, Shantanu K. Dixit
10.5120/ijca2015906278

Prabhavati D. Bahirgonde, Shantanu K. Dixit . Ber Analysis of Turbo Code Interleaver. International Journal of Computer Applications. 126, 14 ( September 2015), 1-4. DOI=10.5120/ijca2015906278

@article{ 10.5120/ijca2015906278,
author = { Prabhavati D. Bahirgonde, Shantanu K. Dixit },
title = { Ber Analysis of Turbo Code Interleaver },
journal = { International Journal of Computer Applications },
issue_date = { September 2015 },
volume = { 126 },
number = { 14 },
month = { September },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume126/number14/22617-2015906278/ },
doi = { 10.5120/ijca2015906278 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:17:25.683698+05:30
%A Prabhavati D. Bahirgonde
%A Shantanu K. Dixit
%T Ber Analysis of Turbo Code Interleaver
%J International Journal of Computer Applications
%@ 0975-8887
%V 126
%N 14
%P 1-4
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a low complexity interleaver design that facilitates high throughput Turbo decoding required for next generation wireless systems. When a parallel decoder structure is considered, interleaver design is the most important issue. In such parallel decoder, the contention problem occurs when more than one extrinsic value references to the same memory block for read or write purpose. This paper focuses on the alternate method for QPP interleaver which shows improved BER performance for large frame size. Bit reversed indexing is used to generate interleaved addresses. A counter is used to generate sequential address as well as interleaved address. The number of address lines of memory which stores data , depends upon frame size of data. In this paper, a comparison is made between best proved interleaver and proposed interleaver on the basis of BER performance for different number of iterations, different frame size and different decoding algorithms.

References
  1. Qu Wei, Information theory and coding theory ,Sciences Publishing House,2005
  2. A. Nimbalkar, Blankenship T. K., Classen B., Fuja T. E., Costello D. J., “ Contention –Free Interleavers for High-Throughput Turbo Decoding”, IEEE transactions on communication, vol. 56, No.8, 2008.
  3. O.Y.Takeshita,”On maximum contention free interleavers and permutation polynomial over integer rings,” IEEE transaction on information theory, vol.52, no.3, 2006.
  4. Yang Sun, Joseph R. Cavallaro, “Efficient hardware implementation of highly-parallel 3GPP LTE/LTE-advance turbo decoder”, INTEGRATION, the VLSI journal 44 (2011) 305-315.
  5. Chixiang Ma, Ping Lin, “Efficient implementation of Quadratic Permutation Polynomial Interleaver in Turbo Codes”, International conference on WCSP 2009.
  6. Yang Sun, Joseph R. Cavallaro, Yuming Zhu, and Manish Goel “Configurable and Scalable Turbo Decoder for 4G Wireless receivers”, 2010
  7. Michal Sybis and Piotr Tyczka, “Reduced complexity Log- MAP algorithm with Jensen inequality based non-recursive max* operator for turbo TCM decoding” EURASIP Journal on Wireless Communications and Networking 2013, 2013:238.
Index Terms

Computer Science
Information Sciences

Keywords

QPP BER APP MAP