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VHDL Implementation of Fast Multiplier based on Vedic Mathematic using Modified Square Root Carry Select Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 127 - Number 2 |
| Year of Publication: 2015 |
| Authors: Heena Goyal, Shamim Akhter |
10.5120/ijca2015906331
|
Heena Goyal, Shamim Akhter . VHDL Implementation of Fast Multiplier based on Vedic Mathematic using Modified Square Root Carry Select Adder. International Journal of Computer Applications. 127, 2 ( October 2015), 24-27. DOI=10.5120/ijca2015906331
Abstract
In this paper, a novel technique for multiplication is presented using Vedic multiplier. Vedic multiplier uses adders and hence making fast adder will increase the overall speed for multiplication. We have done comparative analysis for multiplication using different architectures of adder. For comparison we have taken Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA). We have proposed Vedic multiplication using Modified SQRT-CSA. VHDL design in proposed and synthesis is performed on Virtex-4 FPGA.
References
- Shamim Akhter, "VHDL Implementation of Fast NxN Multiplier Based on Vedic Mathematic," Proc. of 18th European Conference on Circuit Theory and Design (ECCTD), pp. 472-475, Aug. 2007.
- Y. He, C.H. Chang, and J. Gu, “An Area Efficient 64-Bit Square Root Carry-Select Adder for Low Power Applications,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS-2005), vol. 4, pp. 4082-4085, May 2005.
- N. H. E. Weste, D. Harris, and A. Banerjee, “CMOS VLSI Design: A Circuits and Systems Perspective,” Pearson Education, 3rd Edition, 2005.
- B. Ramkumar, and H. M. Kittur, “Low-Power and Area- Efficient Carry Select Adder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb. 2012.
- Shamim Akhter, S. Chaturvedi, and K.Pardhasardi, “CMOS Implementation of Efficient 16-Bit Square Root Carry-Select Adder,“ 2nd International Conference on Signal Processing and Integrated Networks (SPIN), India, Noida, pp. 891 – 896, Feb 2015.
- G.Singh , “Design of Low Area and Low Power Modified 32-BIT Square Root Carry Select Adder”, International Journal of Engineering Research and General Science Volume 2, Issue 4, 2014, pp-422-431.
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