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Performance Analysis of Full Adder Circuit using Double Gate MOSFET
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 129 - Number 12 |
| Year of Publication: 2015 |
| Authors: Mohit Chopra, Navneet Gill, Harjeet Singh |
10.5120/ijca2015907053
|
Mohit Chopra, Navneet Gill, Harjeet Singh . Performance Analysis of Full Adder Circuit using Double Gate MOSFET. International Journal of Computer Applications. 129, 12 ( November 2015), 28-33. DOI=10.5120/ijca2015907053
Abstract
This paper presents a design of a one bit full adder cell based on stack effect using Double Gate MOSFET. This design has been compared with existing one-bit full adder which is designed using power gating technique. In this paper, the proposed circuit has been analyzed for parameters like- power consumption and power delay product. The simulations of the proposed Full Adder have been performed using Tanner EDA Tool version 13.0. All the proposed design simulations are carried out at 45nm technology for various inputs like supply voltage and input voltage. The decrease of 99.5% in power utilization has observed in proposed circuit. The results show a legality of double gate MOSFETs for designing for low power full adder circuit.
References
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