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Design and Optimization of Medium Access Control Protocol of IEEE 802.3 Transmitter with VHDL

by Puran Gour, Ravi Shankar Mishra, Saima Khan, Rajesh Nema
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 13 - Number 1
Year of Publication: 2011
Authors: Puran Gour, Ravi Shankar Mishra, Saima Khan, Rajesh Nema
10.5120/1747-2381

Puran Gour, Ravi Shankar Mishra, Saima Khan, Rajesh Nema . Design and Optimization of Medium Access Control Protocol of IEEE 802.3 Transmitter with VHDL. International Journal of Computer Applications. 13, 1 ( January 2011), 8-12. DOI=10.5120/1747-2381

@article{ 10.5120/1747-2381,
author = { Puran Gour, Ravi Shankar Mishra, Saima Khan, Rajesh Nema },
title = { Design and Optimization of Medium Access Control Protocol of IEEE 802.3 Transmitter with VHDL },
journal = { International Journal of Computer Applications },
issue_date = { January 2011 },
volume = { 13 },
number = { 1 },
month = { January },
year = { 2011 },
issn = { 0975-8887 },
pages = { 8-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume13/number1/1747-2381/ },
doi = { 10.5120/1747-2381 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:01:36.010538+05:30
%A Puran Gour
%A Ravi Shankar Mishra
%A Saima Khan
%A Rajesh Nema
%T Design and Optimization of Medium Access Control Protocol of IEEE 802.3 Transmitter with VHDL
%J International Journal of Computer Applications
%@ 0975-8887
%V 13
%N 1
%P 8-12
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The purpose of this paper is to design and develop a MAC Transmitter on Field Programmable Gate Arrays (FPGA) that converts 32 bit data in to 4 bit DATA for transmitter. In this paper we design the Ethernet (802.3) connection oriented LAN Medium Access Control Transmitter (MAC). It starts by describing the behavior of MAC circuit using VHISC Hardware Description Language (VHDL). A synthesized VHDL model of the chip is developed and implemented on target technology. This paper will concentrate on the testability features that increase product reliability. It focuses on the design of a MAC Transmitter chip with embedded Built-In-Self- Test (BIST) architecture using FPGA technology.

References
  1. Dr. M.S. Sutaone “Performance Evaluation of VHDL Coding Techniques for Optimized Implementation of IEEE 802.3” IEEE transaction on communication, pp- 287-293,Jan 12, 2008
  2. Fedrico Cali, Marco Conti, and Enrico Gregori “ IEEE 802.11 protocol: design and performance evaluation of an adaptive Back off mechanism” IEEE journal on selected areas in communications, vol .18.No.September 2000,pp1774-1778.
  3. P.M.Soni and a Chockalingam “IEEE analysis of link layer backoff schemes on Point –to-point Markov fading links” ,IEEE Transaction on communication, vol.51,no.1, January 2003,pp 29-31.
  4. IEEE 802.3 Cyclic Redundancy Check, Xilinx, XAPP209 (v1.0) march 23, Application note: vertex series and vertex II family, 2001, Author by Chriss Borelli
  5. Kenneth J.Christensen “A simulation study of enhanced arbitration methods for improving Ethernet performance” computer communications,21(1998)24-36, ELSEVIER.
  6. Douglas J. Smith ”HDL Chip Design A Practical Guide for designing ,synthesis & simulating ASICs & FPGAs using VHDL or Verilog”,3rd edition –MGH.pp179-183 and 198-201.
  7. Neil H.E.Weste and David Harris, ”CMOS VLSI Dsign A circuitand systems perspective”3rd edition –PIE,pp164-166.
  8. Paran Kurup & Taher Abbasi Kluwar, “Logic synthesis using synopsys”by,Academic publishers,pp. 39 & pp. 135-142.
Index Terms

Computer Science
Information Sciences

Keywords

Local Area Network (LAN) Medium Access Control(MAC) Linear feed Back Register Logical Link Control(LLC) VHISC Hardware Description Language (VHDL)