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Novel and Efficient Cellular Automata based Symmetric Key Encryption Algorithm for Wireless Sensor Networks

by K.J. Jegadish Kumar, K. Chenna Kesava Reddy, S. Salivahanan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 13 - Number 4
Year of Publication: 2011
Authors: K.J. Jegadish Kumar, K. Chenna Kesava Reddy, S. Salivahanan
10.5120/1767-2424

K.J. Jegadish Kumar, K. Chenna Kesava Reddy, S. Salivahanan . Novel and Efficient Cellular Automata based Symmetric Key Encryption Algorithm for Wireless Sensor Networks. International Journal of Computer Applications. 13, 4 ( January 2011), 30-37. DOI=10.5120/1767-2424

@article{ 10.5120/1767-2424,
author = { K.J. Jegadish Kumar, K. Chenna Kesava Reddy, S. Salivahanan },
title = { Novel and Efficient Cellular Automata based Symmetric Key Encryption Algorithm for Wireless Sensor Networks },
journal = { International Journal of Computer Applications },
issue_date = { January 2011 },
volume = { 13 },
number = { 4 },
month = { January },
year = { 2011 },
issn = { 0975-8887 },
pages = { 30-37 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume13/number4/1767-2424/ },
doi = { 10.5120/1767-2424 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:01:52.365570+05:30
%A K.J. Jegadish Kumar
%A K. Chenna Kesava Reddy
%A S. Salivahanan
%T Novel and Efficient Cellular Automata based Symmetric Key Encryption Algorithm for Wireless Sensor Networks
%J International Journal of Computer Applications
%@ 0975-8887
%V 13
%N 4
%P 30-37
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Our proposed L2D-CASKE:The lightweight 2-dimensional (2-D) cellular automata(CA) based symmetric key encryption algorithm of a 128 bit length that accepts a key length of 128 bits have been designed as lightweight encryption algorithm. As being light weight, it can be easily applied on small devices such as wireless sensor motes, smart cards and other PDAs. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in round. In this paper, the functionality of our proposed algorithm was verified using MATLAB tools and hardware implementation of the algorithm using Field Programmable Gate arrays (FPGAs) are presented. For this purpose, an iterative loop design of our proposed algorithm is presented and implemented on FPGA. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding. Our efficient implementation achieves lower area, and considerably higher throughputs by synthesizing on the target platform Virtex-4 XC4VL25 -10ff668 in Xilinx 9.1

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Index Terms

Computer Science
Information Sciences

Keywords

Cellular automata Symmetric Encryption FPGAs VHDL

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