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Reseach Article

Low Power and High Performance Structures for Fast Fourier Transform Processor

by Anwar Bhasha Pattan, M. Madhavi Latha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 132 - Number 10
Year of Publication: 2015
Authors: Anwar Bhasha Pattan, M. Madhavi Latha
10.5120/ijca2015907619

Anwar Bhasha Pattan, M. Madhavi Latha . Low Power and High Performance Structures for Fast Fourier Transform Processor. International Journal of Computer Applications. 132, 10 ( December 2015), 27-29. DOI=10.5120/ijca2015907619

@article{ 10.5120/ijca2015907619,
author = { Anwar Bhasha Pattan, M. Madhavi Latha },
title = { Low Power and High Performance Structures for Fast Fourier Transform Processor },
journal = { International Journal of Computer Applications },
issue_date = { December 2015 },
volume = { 132 },
number = { 10 },
month = { December },
year = { 2015 },
issn = { 0975-8887 },
pages = { 27-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume132/number10/23631-2015907619/ },
doi = { 10.5120/ijca2015907619 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:29:01.211076+05:30
%A Anwar Bhasha Pattan
%A M. Madhavi Latha
%T Low Power and High Performance Structures for Fast Fourier Transform Processor
%J International Journal of Computer Applications
%@ 0975-8887
%V 132
%N 10
%P 27-29
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Fast Fourier Transform (FFT) being the most important block in many signal processing and communication systems, consumes more power due to its huge computational complexity. Hence, low power design for FFT hardware gains the focus of researchers now-a-days. There are many algorithms and architectures proposed in the literature to achieve lower computational complexity and power dissipation. In this work, some of the best suitable algorithms and architectures for hardware implementation are analyzed in terms of complexity, speed and power consumption by using Xilinx ISE tools and proposed a low power and high performance architecture and algorithm combination for FFT computations.

References
  1. P. Duhamel and M. Vetterli "Fast Fourier transforms: a tutorial review and a state of the art", Signal Process.vol. 19, no. 4, pp. 259-299, Elsevier, 1990.
  2. Tzi-Dar Chiueh, Pei-Yun Tsai, “OFDM baseband receiver design for wireless communications”, John Wiley & Sons (Asia) Pte Ltd, 2007.
  3. J. W. Cooley and J. Tukey, “An algorithm for machine calculation of complex Fourier series”, Math. Comput., vol. 19, pp. 297–301, Apr.1965.
  4. G.D. Bergland, "A Fast Fourier Transform algorithm using base 8 iterations", Math. Comp., Vol. 22, No. 2, April 1968, pp. 275-279
  5. B. M. Baas, ‘A low-power, high-performance, 1024-point FFT processor’, IEEE J. Solid-State Circuits, Vol. 34, No. 3, Mar. 1999, pp. 380–387.
  6. S. He and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation”, in Proc. of IEEE URSI International Symposium on Signals, Systems, and Electronics, Sep. 1998, pp. 257–262.
  7. J. Bhaskar, “A VHDL Primer”, Third Edition, PHI, 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Architecture Computational complexity FFT Low power.