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An Enhanced Secured FPGA based DES

by Shivangi Vajpayee, Braj Bihari Soni
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 133 - Number 2
Year of Publication: 2016
Authors: Shivangi Vajpayee, Braj Bihari Soni
10.5120/ijca2016907145

Shivangi Vajpayee, Braj Bihari Soni . An Enhanced Secured FPGA based DES. International Journal of Computer Applications. 133, 2 ( January 2016), 7-11. DOI=10.5120/ijca2016907145

@article{ 10.5120/ijca2016907145,
author = { Shivangi Vajpayee, Braj Bihari Soni },
title = { An Enhanced Secured FPGA based DES },
journal = { International Journal of Computer Applications },
issue_date = { January 2016 },
volume = { 133 },
number = { 2 },
month = { January },
year = { 2016 },
issn = { 0975-8887 },
pages = { 7-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume133/number2/23756-2016907145/ },
doi = { 10.5120/ijca2016907145 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:29:59.626851+05:30
%A Shivangi Vajpayee
%A Braj Bihari Soni
%T An Enhanced Secured FPGA based DES
%J International Journal of Computer Applications
%@ 0975-8887
%V 133
%N 2
%P 7-11
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper we demonstrate an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on FPGA of device VirtexEXCV400e. As a strategy to reduce the associated design critical path, we utilized a parallel structure that allowed us to compute all the eight DES S-boxes simultaneously. The testing of theimplemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. Whenpipelined approach is employed on the other hand, 17 clocksignals are required for the initial phase only, and one clocksignal is sufficient afterwards for each data generation cycle. TheVery High Speed Integrated Circuit Hardware DescriptionLanguage (VHDL) is used to program the design.

References
  1. Davio, M., Desmedt, Y., Goubert, J., Hoornaert, F., Quisquater, J.J.: Efficient hardware and software implementations for the DES. In: Proc. of Crypto’ 83.(1984) 144–146
  2. Feldmeier, D.C. A high speed crypt program (1989) Technical Memo TM-ARH-013711.
  3. Karn, P.R. (Karns DES implementation source code)
  4. Bishop, M.: An application of a fast data encryption standard implementation.In: Computing Systems, 1(3). (1988) 221–254
  5. Biham, E.: A fast new DES Implementation in Software. In: 4th Int. Workshop on Fast Software Encryption, FSE97, Haifa, Israel, Springer-Verlag, 1997 (1997) 260–271
  6. Eberle, H., Thacker, C.: A 1 Gbit/second GaAs DES chip. In: Proc. IEEE 1992 Custom Integrated Circuits Conference, New York,USA, Springer-Verlag, 1992 (1992) 19.7/1–4
  7. Eberle, H.: A high speed DES implementation for network applications. In: Advances in Cryptology-CRYPTO‘92, Lecture Notes in Computer Science, Berlin, Germany, Springer-Verlag, 1992 (1992) 521–539
  8. Wilcox, D., Pierson, L., Robertson, P., Witzke, E.L., Gass, K.: A DES asic suitable for network encryption at 10 Gbs and beyond. In: CHESS 99, LNCS 1717 (1999) 37–48
  9. Leonard, J., Magione-Smith, W.: A case study of partially evaluated hardware circuits: key specific des. In: Proc. Field-Programmable Logic and Applications,FPL’ 97, London, UK, Springer-Verlag, 1997 (1997) 234–247
  10. Wong, K., Wark, M., Dawson, E.: A Single-Chip FPGA Implementation of the Data Encryption Standard (des) Algorithm. In: IEEE Globecom Communication Conf., Sydney, Australia (1998) 827–832
  11. Kaps, J., Paar, C.: Fast DES implementations for FPGAs and its application to a Universal key-search machine. In: Proc. 5th Annual Workshop on selected areas in cryptography-Sac’ 98, Ontario, Canada, Springer-Verlag, 1998 (1998) 234–247
  12. Core(2000), F.D.: (2000) URL: http://www.free-ip.com/DES/.
  13. McLoone, M., McCanny, J.: High-performance FPGA implementation of DES using a novel method for implementing the key schedule. IEE Proc.: Circuits, Devices & Systems 150 (2003) 373–378
  14. Patterson, C.: High Performance DES Encryption in Virtex FPGAs using Jbits.In: Field-programmable custom computing machines, FCCM’ 00, Napa Valley, CA, USA, IEEE Comput. Soc., CA, USA, 2000 (2000) 113–121
  15. NIST: Announcing the ADVANCED ENCRYPTION STANDARD(AES). Federal Information Standards Publication (2001)
  16. X9.62, A. Federal Information Processing Standard (FIPS) 46, National Bureau Standards (1977)
  17. (Revised):, A.X. National Standards for financial institution key management (wholesale), American Bankers Association (1986)
  18. 8732:, I.D. Banking-key management (wholesale), Association for Payment Clearing Services (1987)
  19. Schneier, B.: Applied Cryptography: Protocols, Algorithms, and Source Code in C. John Wiley & Sons, New York (1996)
  20. Menezes, A., Oorschot, P.V., Vanstone, S.: Handbook of Applied Cryptography. CRC Press, Boca Raton, FL (1997)
  21. Trappe, W., Washington, L.: Introduction to Cryptography with Coding Theory. Prentice Hall, Inc., Upper Saddle River, NJ 07458 (2002)
Index Terms

Computer Science
Information Sciences

Keywords

DES FPGA Parallel structure.

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