Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique
![]() |
10.5120/ijca2016908500 |
Anshu Gupta, Lalita Gupta and R K Baghel. Article: Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique. International Journal of Computer Applications 135(9):22-29, February 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX
@article{key:article, author = {Anshu Gupta and Lalita Gupta and R.K. Baghel}, title = {Article: Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique}, journal = {International Journal of Computer Applications}, year = {2016}, volume = {135}, number = {9}, pages = {22-29}, month = {February}, note = {Published by Foundation of Computer Science (FCS), NY, USA} }
Abstract
This paper presents a capacitor-less low drop-out (LDO) regulator with current mode transconductance amplifier & slew-rate enhancement circuit. The proposed current mode transconductance amplifier as error amplifier improves the slew rate & slew- rate enhancement circuit further senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, transient response of LDO has been further improved using these techniques. The proposed LDO regulator will be designed and simulated in 180nm CMOS technology.
References
- G.A. Rincon-Mora, P.E. Allen.Optimized frequency- shaping circuit topologies for LDO’s. IEEE Trans Circuits Syst II, Analog Digit. Signal Process. vol.45, no.6, pp.703-708, Jun.1998.
- K.N. Leung, P.K.T. Mok.A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE J Solid- State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003.
- R.J.Milliken, J.Silva-Mart´nez, E. S´anchez- Sinencio.Full on-chip CMOS low-dropout voltage regulator. IEEE Trans Circuits Syst I, Reg. Papers, vol.54, no.9, pp.1879-1890, Sept. 2007.
- W.H.Hung, S.H.Lung, and S.I.Liu. A capacitor-freeCMOS low dropout regulator with slew rate enhancement. In Int. symposium on VLSI Design, Automation and Test, 2006, pp.1-4
- C.M.Chen,and C.C.Hung.A capacitor-free CMOS low-dropout voltage regulator. In IEEE Int.symposium on circuits and systems,2009, pp.2525-2528.
- X. Liu, S. Guo, and Y.C. Chang. Design of off-chip capacitor-free CMOS low-dropout voltage regulator. In IEEE Asia Pacific conference on circuits and systems, 2008, pp.1316-1319.
- E.N.Y. Ho, and P.K.T. Mok. A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application. IEEE Trans Circuits Syst II:express briefs. Vol.57, no.2, pp.80-84, Feb. 2010.
- T.Y. Man, K.N. Leung, C.Y. Leung, P.K.T. Mok, and M. Chan. Development of single-transistor- control LDO based on flipped voltage for SoC. IEEE Trans Circuits Syst I, Reg. Papers, vol.55, no.5, pp.1392-1401, Jun. 2008.
- P.Y. Or, and K.N. Leung. An output-capacitorless low- dropout regulator with direct voltage-spike detection. IEEE J Solid-State Circuits, vol.45, no.2, pp.458-466, Feb. 2010.
- K. N. Leung and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no. 10, pp. 1691–1702, Oct. 2003.
- S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low- dropout regulator for SoC with Q-reduction,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 658–664, Mar. 2007.
- Milliken, R.J.; Silva-Martinez, J.; Sanchez Sinencio, E.; "Full On-Chip CMOS Low-Dropout Voltage Regulator," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.54, no.9, pp.1879-1890, Sept. 2007.
- P. Hazucha, T. Karnik, B. A. Bradley, C. Parsons, D. Finan, and S. Borkar, “Area-efficient linear regulator with ultra-fast load regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005.
- Y.-H. Lam and W.-H. Ki, “A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 442–443, 626.
- Ali Enayat Zadeh and Yung-I Chang, “Linear voltage regulator using adaptive biasing”, United States Patent US 6,522,111 B2, February 18, 2003 (United States Patent Application no. US 2002/0130646 A1 September 19, 2002).
- Jaideep Banerjee and Tushar S Nandurkar, “Voltage regulator with improved load regulation using adaptive biasing”, United States Patent US 6,933,772 B1, August 23, 2005.
- Matthias Eberlein, “Adaptive biasing concept for current mode voltage regulators”, United States Patent US 7,166,991 B2, January 23, 2007.
- T. Y. Man, P. K. T. Mok, and M. Chan, “A high slew- rate push-pull output amplifier for low- quiescent current low-dropout regulators with transient-response improvement,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 54, no. 9, pp. 755–759, Sep. 2007.
- P. Y. Or and K. N. Leung, “An output capacitorless low- dropout regulatorwith direct voltage-spike detection,” IEEE J. Solid-State Circuits, vol. 45,no. 2, pp. 458–466, Feb. 2010.
Keywords
Dynamic biasing, current mode transconductance amplifier.