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Reseach Article

Linear Feed Back Shift Register Base Multiple Long Period Random Binary Sequences Generator

by Neha Agrawal, Neelesh Gupta, Neetu Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 138 - Number 3
Year of Publication: 2016
Authors: Neha Agrawal, Neelesh Gupta, Neetu Sharma
10.5120/ijca2016908727

Neha Agrawal, Neelesh Gupta, Neetu Sharma . Linear Feed Back Shift Register Base Multiple Long Period Random Binary Sequences Generator. International Journal of Computer Applications. 138, 3 ( March 2016), 13-16. DOI=10.5120/ijca2016908727

@article{ 10.5120/ijca2016908727,
author = { Neha Agrawal, Neelesh Gupta, Neetu Sharma },
title = { Linear Feed Back Shift Register Base Multiple Long Period Random Binary Sequences Generator },
journal = { International Journal of Computer Applications },
issue_date = { March 2016 },
volume = { 138 },
number = { 3 },
month = { March },
year = { 2016 },
issn = { 0975-8887 },
pages = { 13-16 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume138/number3/24358-2016908727/ },
doi = { 10.5120/ijca2016908727 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:38:41.125496+05:30
%A Neha Agrawal
%A Neelesh Gupta
%A Neetu Sharma
%T Linear Feed Back Shift Register Base Multiple Long Period Random Binary Sequences Generator
%J International Journal of Computer Applications
%@ 0975-8887
%V 138
%N 3
%P 13-16
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In electronics communication systems random number generation is use for security purpose. The numbers which are in random but in predefined sequence pattern is called as pseudo random while the numbers which are unpredictable and in undefined sequence pattern is called as true random numbers. These random numbers are also use for bit error rate testinig (BERT). When multiple bits are required then linear feedback shift registers are the best source of random number generator. The increase in length of random number sequence consumes more area. Here a increase lenth of sequence and multiple bits random number generator is design using linear feedback shift registers and multiple port SRAM memory. The SRAM base random number generator is area efficient using VHDL. The improved computational time and throughput is computed using VHDL implementation.

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Index Terms

Computer Science
Information Sciences

Keywords

RNG BERT LFSR SRAM