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High Speed Architecture for KECCACK Secure Hash Function

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Pasupuleti Sailaja, Mahendra Vucha
10.5120/ijca2016909237

Pasupuleti Sailaja and Mahendra Vucha. Article: High Speed Architecture for KECCACK Secure Hash Function. International Journal of Computer Applications 139(9):19-24, April 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Pasupuleti Sailaja and Mahendra Vucha},
	title = {Article: High Speed Architecture for KECCACK Secure Hash Function},
	journal = {International Journal of Computer Applications},
	year = {2016},
	volume = {139},
	number = {9},
	pages = {19-24},
	month = {April},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

Cryptography is a technique that protects the information, which is in transit or in storage, from unauthorized or unexpected reveals. This paper demonstrates a Secure Hash Algorithm-3(SHA-3) called Keccack, and also proposeda hardware architecture for the Keccack to support high speed security application. Since SHA-3 supports high level of parallelism, the proposed hardware architecture brings higher speed, in terms of bit rate and capacity, and also provides better security demanded by Internet of Things. This paper also demonstrates the architectural attributes of popular and real life cryptography techniques such as, Secure Hash Algorithm-1 (SHA-1), Secure Hash Algorithm-2 (SHA-2) and Advanced Encryption Standard (AES). In this research, the security techniques AES, SHA-1, SHA-2 and SHA-3 has been implemented on Virtex-5 FPGA device and their architectural attributes were captured. Finally, the proposed architecture of SHA-3 is compared with architecture of ontemporary security techniques(AES, SHA-1, and SHA-2) in terms of speed, area and power. The comparison results shown that the SHA-3 architecture brought optimum performance over its contemporary security techniques.

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  20. AUTHORS PROFILE
  21. Pasupuleti Sailaja received her MSc(Tech) in VLSI fromAndhra University in 2013. She is currently pursuing herM.Tech (Communication Systems) in Christ University,Bangalore. Her area of interests are VLSI and Cryptography.
  22. Mahendra Vucha received his B. Tech in Electronics & Communication Engineering from JNTU, Hyderabad in 2007 and M. Tech degree in VLSI and Embedded System Design from MANIT, Bhopal in 2009. He also received Ph. D degree in Electronic and Communication Engineering from MANIT, Bhopal (M.P), India. He is currently working as Asst. Prof in Department of Electronic and Communication Engineering at Faculty of Engineering, Christ University, Bangalore.His areas of interest are Hardware Software Co-Design, Analog Circuit design, Digital System Design and Embedded System Design.

Keywords

Internet of Things, Secure Hash Algorithm, Filed Programmable Gate Array.