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Reseach Article

Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications

by Akanchha Rusia, Soumitra S. Pande
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 151 - Number 11
Year of Publication: 2016
Authors: Akanchha Rusia, Soumitra S. Pande
10.5120/ijca2016911930

Akanchha Rusia, Soumitra S. Pande . Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications. International Journal of Computer Applications. 151, 11 ( Oct 2016), 1-4. DOI=10.5120/ijca2016911930

@article{ 10.5120/ijca2016911930,
author = { Akanchha Rusia, Soumitra S. Pande },
title = { Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications },
journal = { International Journal of Computer Applications },
issue_date = { Oct 2016 },
volume = { 151 },
number = { 11 },
month = { Oct },
year = { 2016 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume151/number11/26274-2016911930/ },
doi = { 10.5120/ijca2016911930 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:56:48.492268+05:30
%A Akanchha Rusia
%A Soumitra S. Pande
%T Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 151
%N 11
%P 1-4
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Counter Hold time Finite State Machine Registers Storage Element.