Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

Simulation and Investigation on “Effect of Dependency in under Pipelining”

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Renuka Patel, Sanjay Kumar

Renuka Patel and Sanjay Kumar. Simulation and Investigation on “Effect of Dependency in under Pipelining”. International Journal of Computer Applications 152(6):12-15, October 2016. BibTeX

	author = {Renuka Patel and Sanjay Kumar},
	title = {Simulation and Investigation on “Effect of Dependency in under Pipelining”},
	journal = {International Journal of Computer Applications},
	issue_date = {October 2016},
	volume = {152},
	number = {6},
	month = {Oct},
	year = {2016},
	issn = {0975-8887},
	pages = {12-15},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2016911877},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Instruction level parallelism is the most common technique to achieve speedup and Pipelining is one of the techniques to achieve Instruction level parallelism. Pipelining is of 5 types – Scalar pipelining, Superscalar pipelining, Super pipelining, Under pipelining and Super Scalar Super pipelining. In pipelining technique more than one instruction can issue simultaneously into different functional unit. But, dependency is most common problem in pipelining. This paper shows the development of simulator using ‘C’ language to study the effect of dependency in under pipelining. This paper also calculates some pipelining parameters like CPI, IPC etc.


  1. Anish Gupta,Vinayak Kini, Prathik Shetty “Five staged pipelined processor with self clocking mechanism”, ISBN: 978-1-4673-7910-6 USB ISBN: 978-1-4673-7909-0, IEEE Xplore, JAN 14 2016.
  2. M. Flynn, Computer Architecture—Pipelined and Parallel Processor Design, Jones and Bartlett Publishers, Boston, 1995
  3. Martti forsell” Implementation of Instruction Level and Thread Level Parallelism in Computers” ISSN 1238-6944, ISBN 951-708-557-5, pp 3.
  4. L John. Hennessy ,“VLSI Processor Architecture”, IEEE Transactions on Computers, VOL. c-33, No. 12, December 1984
  5. Simran Rana Rajesh Mehra “Hyper Pipelined RISC Processor Implementation- A Review”,International Journal of Engineering Research & Technology (IJERT) Vol. 2 Issue 10, October - 2013 IJERTIJERT ISSN: 2278-0181
  6. Jouppi N. P. and Wall D. W., “Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines” Digital Western Research Laboratory, Tech. Rep. 89/7, Jul. 1989
  7. Hwang K.,“Advanced Computer Architecture” Tata Mc Graw Hill 2001, pp 160, 54,
  8. Stallings W. ,”Computer Organization and Architecture ” Pearson Education 2010, ISBN 978-81-7758-993-1, pp 504-510
  9. Johnson W.M., “Super-Scalar Processor Design” Technical Report No.CSL-TR-89-383, June 1989, pp 8-9.
  10. Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi “Dynamic Speculation and Synchronization of Data Dependences”, Proceedings of the 24th Annual International Symposium on Computer Architecture.
  11. Henry Styles, David Barrie Thomas and Wayne Luk ,“Pipelining Designs with Loop-Carried Dependencies”,
  12. Saravanan V., Kothari D. P. and Woungang I.,” An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs” Human-centric Computing and Information Sciences , SpringerOpen


Instruction Level Parallelism, Dependency, Pipelining, Simulation, CPI, IPC, MIPS