CFP last date
22 April 2024
Call for Paper
May Edition
IJCA solicits high quality original research papers for the upcoming May edition of the journal. The last date of research paper submission is 22 April 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic

by Harshit Shrivastava, Himanshu Nautiyal
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 153 - Number 6
Year of Publication: 2016
Authors: Harshit Shrivastava, Himanshu Nautiyal
10.5120/ijca2016912084

Harshit Shrivastava, Himanshu Nautiyal . Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic. International Journal of Computer Applications. 153, 6 ( Nov 2016), 41-46. DOI=10.5120/ijca2016912084

@article{ 10.5120/ijca2016912084,
author = { Harshit Shrivastava, Himanshu Nautiyal },
title = { Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic },
journal = { International Journal of Computer Applications },
issue_date = { Nov 2016 },
volume = { 153 },
number = { 6 },
month = { Nov },
year = { 2016 },
issn = { 0975-8887 },
pages = { 41-46 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume153/number6/26409-2016912084/ },
doi = { 10.5120/ijca2016912084 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:58:26.525463+05:30
%A Harshit Shrivastava
%A Himanshu Nautiyal
%T Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 153
%N 6
%P 41-46
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the FPGA implementation of a Decimal Floating Point (DFP) arithmetic unit. The design performs addition, subtraction and multiplication on 64-bit operands that use the IEEE 754-2008 DPD encoding of DFP numbers. The design uses an equal bypass adder, this adder reduces the power consumption and it also reduces the delay by reducing the gate count. The design also uses barrel shifter instead of sequential shifter to reduce delay. Also 64 bit parallel BCD multiplier is used to perform fixed point multiplication. The proposed DFP arithmetic unit supports operations on the decimal64 format and it is easily extendable for the decimal128 format.

References
  1. M.F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proc. IEEE 16th Symp. Computer Arithmetic, pp. 104-111, 2003.
  2. IBM Corporation, The ‘Telco’ benchmark, http://speleotrove.com/ Decimal/telcoSpec.html, 2005.
  3. D.-G. for Economic and F. A. C. from the Commission to the European Council, “Review of the Introduction of Euro Notes and Coins,” EURO PAPERS, Apr. 2002.
  4. M.F. Cowlishaw The decNumber library, v3.68. IBM, http://speleotrove.- com/decimal/decnumber.pdf, 2013.
  5. S. Microsystems BigDecimal Class, Java 2 Platform Standard ed. 5.0, APISpecification,http://docs.oracle.com/javase/1.5.0/docs/api/java/math/BigDecimal.html, 2013.
  6. M. Cornea, C. Anderson, J. Harrison, P.T.P. Tang, E. Schneider, and C.
  7. Tsen, “A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format,” Proc. IEEE 18th Symp.
  8. ANSI/IEEE 754-1985, “Standard for Binary Floating-Point Arithmetic”.
  9. R.K. Yu, G.B. Zyner, 167 MHz radix-4 floating point multiplier, Proceedings 12th Symposium on Computer Arithmetic, 1995, pp. 149-154.
  10. C. Gamez, R. Pang, Apparatus and method for rounding operands, U.S. patent 5258943, 1993.
  11. M. Saishi, T. Minemaru, Multiplication circuit having rounding function, U.S. patent 5500812, 1996.
  12. Guy Even, Silvia M. Mueller, Peter-Michael Seidel “A dual precision IEEE Floating-point multiplier” Elsevier INTEGRATION, the VLSI journal 29 (2000) 167-180.
  13. C. Tsen, M.J. Schulte, and S.G. Navarro, “Hardware Design of a Binary Integer Decimal Based IEEE P754 Rounding Unit,” Proc. IEEE 18th Int’l Conf. Application-Specific Systems, Architectures and Processors, pp. 115-121, 2007.
  14. B.J. Hickmann, A. Krioukov, M.J. Schulte, and M.A. Erle, “A Parallel IEEE P754 Decimal Floating-Point Multiplier,” Proc. IEEE 25th Int’l Conf. Computer Design, 2007.
  15. C. Tsen, S.G. Navarro, M.J. Schulte, B. Hickmann, and K. Compton, “A Combined Decimal and Binary Floating-Point Multiplier,” Proc. IEEE 20th Int’l Conf. Application-Specific Systems, Architectures, and Processors, pp. 8-15, 2009.
  16. J. Di and J. S. Yuan, “Power-aware pipelined multiplier design based on 2-dimensional pipeline gating,” in 13th Great Lakes Symposium on VLSI. ACM, 2003, pp. 64–67.
  17. Sunjoo Hong, Taehwan Roh and Hoi-Jun Yoo, “a 145w 8×8 parallel multiplier based on optimized bypassing architecture”, department of electrical engineering, Korea advanced institute of science and technology (KAIST), Daejeon, Republic of Korea, IEEE, pp.1175-1178, 2011.
  18. Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu and Chia-Jen Sheu, “low power multipliers using enhenced row bypassing schemes”, department of electronic engineering, National Yunlin University of science & technology, Touliu, Yunlin, Taiwan, IEEE, pp.136-140, 2007.
  19. George Economakos, Dimitris Bekiaris and Kiamal Pekmestzi, “a mixed style architecture for low power multipliers based on a bypass technique”, national technical University of Athens, school of electrical and computer engineering, heroon polytechniou 9, GR-15780 Athens, Greece, IEEE, pp.4-6, 2010.
  20. Meng-Lin Hsia and Oscal T.-C. Chen, “low power multiplier optimized by partial-product summation and adder cells”, dept. of electrical engineering, national chung cheng University, chia-yi, 621, Taiwan, IEEE, pp.3042-3045, 2009. P. C. H. Meier, “analysis and design of low power digital multipliers”, Ph.D. thesis, Carnegie Mellon University, dept. of electrical and computer engineering, Pittsburgh, Pennsylvania, 1999.
  21. Carlos Minchola, Martin Vazquez and Gustavo Sutter “A FPGA IEEE 754 2008 decimal floating point adder subtractor” 2011 IEEE.
  22. Yanyu Ding, Deming Wang, Jianguo Hu and Hongzhou Tan, “A Low power Parallel Multiplier Based on Optimized-Equal-Bypassing-Technique”, Third International Conference on Information Science and Technology March, 2013 IEEE, China
  23. Jaberipur, Ghassem, and Amir Kaivani. "Binary-coded decimal digit multipliers." IET Computers & Digital Techniques 1.4 (2007): 377-381.
Index Terms

Computer Science
Information Sciences

Keywords

Floating point addition Floating point multiplication Floating point subtraction FPGA Delay Area overhead IEEE P754-2008

Powered by PhDFocusTM