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Review Paper on Efficient VLSI Architecture for Carry Select Adder

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Anamika Mandal, Puran Gour, Braj Bihari Soni

Anamika Mandal, Puran Gour and Braj Bihari Soni. Review Paper on Efficient VLSI Architecture for Carry Select Adder. International Journal of Computer Applications 161(4):4-7, March 2017. BibTeX

	author = {Anamika Mandal and Puran Gour and Braj Bihari Soni},
	title = {Review Paper on Efficient VLSI Architecture for Carry Select Adder},
	journal = {International Journal of Computer Applications},
	issue_date = {March 2017},
	volume = {161},
	number = {4},
	month = {Mar},
	year = {2017},
	issn = {0975-8887},
	pages = {4-7},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2017913137},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


A adder is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design many types of adder such as ripple carry adder, carry skip adder, carry a look head adder and carry select adder. Among this adder carry select adder is the high speed, low power consumption and hence less area or even combination of them in adder. However area and speed are two conflicting constraints.


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Ripple Carry Adder, Carry Select Adder (CSLA), Booth Encoder (BEC)