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A Comparative Study on the Power Delay Product of Efficient Adders

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose, Ashly John

Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose and Ashly John. A Comparative Study on the Power Delay Product of Efficient Adders. International Journal of Computer Applications 163(3):33-36, April 2017. BibTeX

	author = {Anjana Jain Tom and Remya Susan John and Sanjana Accamma Kurian and Susan Jose and Ashly John},
	title = {A Comparative Study on the Power Delay Product of Efficient Adders},
	journal = {International Journal of Computer Applications},
	issue_date = {April 2017},
	volume = {163},
	number = {3},
	month = {Apr},
	year = {2017},
	issn = {0975-8887},
	pages = {33-36},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2017913491},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


In realizing modern Very Large Scale Integration (VLSI) circuits, low-power and high- speed are the two predominant factors which need to be considered. There exists a trade-off between the design parameters such as speed, power consumption, and area. Adders are the most comprehensively used components in many circuits and they are building block arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its execution and power optimization is of at most importance. This paper proposes design of fast adders using two new dynamic logics named D3L (Data Driven Dynamic Logic) and sp-D3L (split pre-charge – Data Driven Dynamic Logic). Examination of two circuits, D3l and SP-D3L are made by using the software, Cadence Virtuoso. Power Delay Product (PDP) is calculated for both these logics.


  1. Sohan Purohit, Marco, and Martin Margala, “Design Space Exploration of Split-Path Driven Dynamic Full Adder”, Journal of Low Power Electronics Vol.6,1-13,2010.
  2. G.Karthik Reddy, D.Sharat Babu Rao, “A Comparative study on Low-Power and High Speed Carry Select Adder”, IEEE Sponsored 9th International Conference on Intelligent Systems and Control (ISCO) 2015.
  3. Ms Anagha U P, Mr. Pramod P, Power and Area Efficient Carry Select Adder, IEEE Recent Advances in Intelligent Computational Systems(RAICS) , Dec 2015
  4. Sohan Purohit, Martin Margala, “Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance”, IEEE transactions on Very Large Scale Integration (VLSI) Systems, Vol 20. No. 7, July 2012.
  5. Vivek Kumar, Vrinda Gupta and Rohit Mayura, “A Study and Analysis of High Speed Adder in Power Constrained Environment”, International Journal of Soft Computing and Engineering (IJSCE) , ISSN: 2231-2307 Vol 2,Issue -3, July2012
  6. A. Shams, T. Darwish, and M. Bayoumi, “Performance analysis Of low power 1-bit CMOS full-adder cells”,. IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems 10, 20 (2002).
  7. Rafati R., Fakhraie S.M., Smith K C.: „A 16-bit barrel-shifterimplemented in data-driven dynamic logic (D3L)‟, IEEE Trans. Circuits Syst. I, 2006, 53, (10), pp. 2194–2202
  8. F. Frutaci, M. Lanuzza, P. Zicari S. Perri, P. Corsonello “ Low Power Split Path Data Driven Dynamic Logic” published in IET Circuit Devices & Systems 20th April 2009.


Data Driven Dynamic logic, Split path Data Driven Dynamic, pull-up network (PUN), pull- down network (PDN),Power delay product.