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Reseach Article

A Comparative Study on the Power Delay Product of Efficient Adders

by Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose, Ashly John
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 163 - Number 3
Year of Publication: 2017
Authors: Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose, Ashly John
10.5120/ijca2017913491

Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose, Ashly John . A Comparative Study on the Power Delay Product of Efficient Adders. International Journal of Computer Applications. 163, 3 ( Apr 2017), 33-36. DOI=10.5120/ijca2017913491

@article{ 10.5120/ijca2017913491,
author = { Anjana Jain Tom, Remya Susan John, Sanjana Accamma Kurian, Susan Jose, Ashly John },
title = { A Comparative Study on the Power Delay Product of Efficient Adders },
journal = { International Journal of Computer Applications },
issue_date = { Apr 2017 },
volume = { 163 },
number = { 3 },
month = { Apr },
year = { 2017 },
issn = { 0975-8887 },
pages = { 33-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume163/number3/27379-2017913491/ },
doi = { 10.5120/ijca2017913491 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:09:59.464892+05:30
%A Anjana Jain Tom
%A Remya Susan John
%A Sanjana Accamma Kurian
%A Susan Jose
%A Ashly John
%T A Comparative Study on the Power Delay Product of Efficient Adders
%J International Journal of Computer Applications
%@ 0975-8887
%V 163
%N 3
%P 33-36
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In realizing modern Very Large Scale Integration (VLSI) circuits, low-power and high- speed are the two predominant factors which need to be considered. There exists a trade-off between the design parameters such as speed, power consumption, and area. Adders are the most comprehensively used components in many circuits and they are building block arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its execution and power optimization is of at most importance. This paper proposes design of fast adders using two new dynamic logics named D3L (Data Driven Dynamic Logic) and sp-D3L (split pre-charge – Data Driven Dynamic Logic). Examination of two circuits, D3l and SP-D3L are made by using the software, Cadence Virtuoso. Power Delay Product (PDP) is calculated for both these logics.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Data Driven Dynamic logic Split path Data Driven Dynamic pull-up network (PUN) pull- down network (PDN) Power delay product.