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Diode Switch: A Novel Technique for Mitigation of Leakage Power in DSM Technologies

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Uday Panwar, Himanshu Vishnoi

Uday Panwar and Himanshu Vishnoi. Diode Switch: A Novel Technique for Mitigation of Leakage Power in DSM Technologies. International Journal of Computer Applications 167(14):13-19, June 2017. BibTeX

	author = {Uday Panwar and Himanshu Vishnoi},
	title = {Diode Switch: A Novel Technique for Mitigation of Leakage Power in DSM Technologies},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2017},
	volume = {167},
	number = {14},
	month = {Jun},
	year = {2017},
	issn = {0975-8887},
	pages = {13-19},
	numpages = {7},
	url = {},
	doi = {10.5120/ijca2017914209},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


As technology scales down below 65nm there is a rapid growth in semiconductor industries; reduction in transistor size leads to exponential increase in power consumption in DSM technology. The major concerns of VLSI designers are to develop a circuit which is having high performance with minimal size earlier. The fast growth in portable computing and wireless communication has led to the power dissipation along with heating. In this paper we have implemented a novel leakage reduction technique known as Diode switch (Combination of PMOS and NMOS sleep transistor) and inserted a sleep transistor above PUN and below PDN which increases the resistance of the circuit. By inserting the sleep transistor short circuit power consumption reduces which rail the circuit from supply voltage, but there is penalty of area take place. All the simulation is performed 32nm technology by using HSPICE simulator. Proposed DHS circuit reduce 48.98%, DFS reduces 52.89% and DHFS reduces upto 68.27% of leakage power.


  1. K.Roy and S.C.Prasad, “Low-power CMOS VLSI ciruit design”. New York: Wiley, 2000, ch. .5, pp.214-219.
  2. Y.Taur, T.H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, New York, 1998.
  3. International Technology Roadmap for Semiconductors (ITRS-05).
  4. Ali Peiravi, Mohammad Asyaei.” Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates” INTEGRATION, the VLSI Journal 45 (2012), pp 22–32.
  5. K. Roy, S.Mukhopadhyay, H. Mahmoodi-meimand, “Leakage tolerant mechan- isms and leakage reduction techniques in deep-submicron CMOS circuits”, Proceedings of the IEEE 91 (2003), pp. 305–327.
  6. M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep submicron Cache Memories,” International Symposium on Low Power Electronics and Design, July 2000, pp. 90-95.
  7. Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” International Symposium on Low Power Electronics and Design, August 1998, pp. 239-244.
  8. Kawaguchi, H., Nose, K., and Sakurai, T. “ A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico ampere Stand-By Current,” IEEE Journal of Solid State Circuits vol.35,n.10, October 2000, pp.1498-1501.
  9. Se Hun Kim, Vincent J. Mooney III, “Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design”
  10. A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis, \Design Considerations and Tools for Low-Voltage Digital System Design," In Proceedings of the 33rd Design Automation Conference, pp. 113{118, 1996}.
  11. J. Kao, A. Chandrakasan, and D. Antoniadis, \Transistor Sizing Issues and Tools for Multi-threshold CMOS Technology," In Proceedings of the 34th Design Automation Conference, pp. 409{414, Las Vegas, Nevada, 1997}.
  12. A. Chandrakasan, J. Kao "MTCMOS sequential circuits, “Proceedings of European Solid-State Circuits Conference, September 2001,pp 332- 335.
  13. Park, J. C., and Mooney III, V. J. “ Sleepy Stack Leakage Reduction,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 14, Nov 2006, pp.1250-1263.
  14. S. Kim and V. Mooney, “The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4 bit Adder,” Technical Report GITCERCS-06- 03, Georgia Institute of Technology, March 2006,
  15. Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, and Alessandro Trifiletti, “Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 2, FEBRUARY 2014.
  16. Ajay Kumar Dadoria, Kavita Khare, R. P. Singh, “A Novel Approach for Leakage Power Reduction in Deep Submicron Technologies in CMOS VLSI Circuits” IEEE International Conference on Computer, Communication and Control (IC4-2015), 2015.
  17. Lokesh Garg and Vineet Sahula, Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 63, No. 5, May 2016.


Leakage Reduction, High speed, Low power, DSM

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