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Implementation and Analysis of Optimized AES on FPGA

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Nikita Purohit, Meghana A. Hasamnis

Nikita Purohit and Meghana A Hasamnis. Implementation and Analysis of Optimized AES on FPGA. International Journal of Computer Applications 169(10):28-30, July 2017. BibTeX

	author = {Nikita Purohit and Meghana A. Hasamnis},
	title = {Implementation and Analysis of Optimized AES on FPGA},
	journal = {International Journal of Computer Applications},
	issue_date = {July 2017},
	volume = {169},
	number = {10},
	month = {Jul},
	year = {2017},
	issn = {0975-8887},
	pages = {28-30},
	numpages = {3},
	url = {},
	doi = {10.5120/ijca2017914899},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


In today’s world of digital transmission and reception of data and images high performance processing hardware is required. This paper presents an optimized AES algorithm for both software and hardware implementation through which the execution speed of the process is improved by reducing the cycle count. Optimized AES is implemented using soft-core processor on FPGA Spartan-6 kit and the results are obtained using timing analyzer tool of Xilinx design suite 14.5. The execution time for hardware implementation of optimized AES code is improved by 12.46% and 11.58% for encryption and decryption module respectively. Target device used for implementation of design is XILINX 14.5 platform studio xc6slx45-2csg324.


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