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Implementation and Analysis of Optimized AES on FPGA

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Nikita Purohit, Meghana A. Hasamnis
10.5120/ijca2017914899

Nikita Purohit and Meghana A Hasamnis. Implementation and Analysis of Optimized AES on FPGA. International Journal of Computer Applications 169(10):28-30, July 2017. BibTeX

@article{10.5120/ijca2017914899,
	author = {Nikita Purohit and Meghana A. Hasamnis},
	title = {Implementation and Analysis of Optimized AES on FPGA},
	journal = {International Journal of Computer Applications},
	issue_date = {July 2017},
	volume = {169},
	number = {10},
	month = {Jul},
	year = {2017},
	issn = {0975-8887},
	pages = {28-30},
	numpages = {3},
	url = {http://www.ijcaonline.org/archives/volume169/number10/28022-2017914899},
	doi = {10.5120/ijca2017914899},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In today’s world of digital transmission and reception of data and images high performance processing hardware is required. This paper presents an optimized AES algorithm for both software and hardware implementation through which the execution speed of the process is improved by reducing the cycle count. Optimized AES is implemented using soft-core processor on FPGA Spartan-6 kit and the results are obtained using timing analyzer tool of Xilinx design suite 14.5. The execution time for hardware implementation of optimized AES code is improved by 12.46% and 11.58% for encryption and decryption module respectively. Target device used for implementation of design is XILINX 14.5 platform studio xc6slx45-2csg324.

References

  1. G. Julius Caesar. Cryptography, Security Engineering: A Guide to Building Dependable Distributed System, Chapter 5.
  2. Tutorials Point www.tutorialspoint.com.
  3. Guru Ghasidas Vishwavidyalaya http://www.ggu.ac.in
  4. Sourabh Chandra and Smita Paira. A comparative study of symmetric and asymmetric key cryptography, ICECCE 2014.
  5. The Rijndeal algorithm T.Jamil, IEEE potential 2004 volume: 23.
  6. J.Daeman , V.Rijmen. the block cipher Rijndeal springer- verlag ,2002.
  7. Panda, Madhumita, and Atul Nag. "Plain Text Encryption Using AES, DES and SALSA20 by Java Based Bouncy Castle API on Windows and Linux."ICACCE, 2015.
  8. A.M.Deshpande, M.S.Deshpande and D.N.kayatanayar, “FPGA Implementation of AES encryption and decryption”. IEEE inter conference, Vol.01, issue 04, pp.1-6, june 2009.
  9. N. S. SAI SRINIVAS and MD. AKRAMUDDIN. “FPGA Based Hardware Implementation of AES Rijndael Algorithm for Encryption and Decryption” International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016.
  10. T.Good, M.Benaissa. Pipelined AES on FPGA with support for feedback. IET Inf. Secur 2007.
  11. Franjo Plavec, “SOFT-CORE PROCESSOR DESIGN” Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2004.
  12. MicroBlaze Processor Reference Guide by Xilinx, 2008
  13. Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores by Michael Hübner, Katarina Paulsson, Jürgen Becker Universitaet Karlsruhe (TH), Germany.
  14. A Compact 8-bit AES Crypto-Processor F Haghighizadeh .H. Attarzadeh, M. Sharifkhani, Second International Conference on Computer and Network Technology,IEEE 2010.
  15. AES-CBC Software Execution OptimizationRazvi Doomun*, Jayramsingh Doma, Sundeep Tengur Computer Science and Engineering, University of Mauritius.

Keywords

FPGA-Spartan 6, Cryptography, AES.