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A Block based Area-Delay Efficient Architecture for Multi-Level Lifting 2-D DWT

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Abhishek Choubey, Basant Kumar Mohanty
10.5120/ijca2017914471

Abhishek Choubey and Basant Kumar Mohanty. A Block based Area-Delay Efficient Architecture for Multi-Level Lifting 2-D DWT. International Journal of Computer Applications 169(4):1-4, July 2017. BibTeX

@article{10.5120/ijca2017914471,
	author = {Abhishek Choubey and Basant Kumar Mohanty},
	title = {A Block based Area-Delay Efficient Architecture for Multi-Level Lifting 2-D DWT},
	journal = {International Journal of Computer Applications},
	issue_date = {July 2017},
	volume = {169},
	number = {4},
	month = {Jul},
	year = {2017},
	issn = {0975-8887},
	pages = {1-4},
	numpages = {4},
	url = {http://www.ijcaonline.org/archives/volume169/number4/27970-2017914471},
	doi = {10.5120/ijca2017914471},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In this paper we have proposed a look-up-table (LUT) based structure for high-throughput implementation of multilevel lifting DWT. The proposed structure can process one block of samples to achieve high-throughput rate. Compared with the best of the similar existing structure, it does not involves any multipliers but it requires more adders and 21504 extra ROM words for J=3; its offers less critical path delay as compared to exiting structure. Synthesis results show that proposed structure has less ADP 56% less area and 13% less power compared to existing structure for block size J=2. Similarly proposed structure has 64% ADP and less power 21% as compared to existing structure for J=3. The proposed structure is fully scalable for higher block-sizes and it can offer flexibility to derive area-delay efficient structures for various applications.

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Keywords

Look up table (LUT), VLSI, lifting, 2-dimensional (2-D) DWT.