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Light Weight Asymmetric Cryptographic Algorithm for Financial Transactions through Mobile Application

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Rina Maria, V. Anitha

Rina Maria and V Anitha. Light Weight Asymmetric Cryptographic Algorithm for Financial Transactions through Mobile Application. International Journal of Computer Applications 170(3):37-41, July 2017. BibTeX

	author = {Rina Maria and V. Anitha},
	title = {Light Weight Asymmetric Cryptographic Algorithm for Financial Transactions through Mobile Application},
	journal = {International Journal of Computer Applications},
	issue_date = {July 2017},
	volume = {170},
	number = {3},
	month = {Jul},
	year = {2017},
	issn = {0975-8887},
	pages = {37-41},
	numpages = {5},
	url = {},
	doi = {10.5120/ijca2017914763},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Nowadays world is seen through mobile internet in a fraction of seconds, which invaded the need for many mobile applications. Financial transactions through mobile phones has become primitive mode of transactions. All these mobile applications including financial transactions demands for better security due to pervasive environment. In our work, we propose light weight Elliptical Curve Cryptographic method suitable for mobile applications. Elliptic curve point multiplication or scalar multiplication is the operation of adding a point P on the elliptic curve to itself successively scalar number of times. This paper describes an algorithm for light weight computation of scalar multiplication for elliptic curves defined over binary fields using projective coordinate system eliminating the need to perform inversions as needed with computations involving affine coordinates. It effectively incorporates fast computation method for binary elliptic curves by making use of Exclusive-OR gates. The effectiveness of the algorithm is measured both by Matlab simulation and Field-Programmable Gate Array (FPGA) implementation. Hardware implementation using Verilog proves that the proposed algorithm consumes less resources in terms of delay and power.


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Vedic multiplier, Urdhva Tirgyagbyham sutra, ECC, conventional array multiplier, FPGA implementation, delay, low power, low area consumption.