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An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
O. E. Haruna, K. A. Abubilal, A. T. Salawudeen
10.5120/ijca2017914844

O E Haruna, K A Abubilal and A T Salawudeen. An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA. International Journal of Computer Applications 170(5):31-38, July 2017. BibTeX

@article{10.5120/ijca2017914844,
	author = {O. E. Haruna and K. A. Abubilal and A. T. Salawudeen},
	title = {An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA},
	journal = {International Journal of Computer Applications},
	issue_date = {July 2017},
	volume = {170},
	number = {5},
	month = {Jul},
	year = {2017},
	issn = {0975-8887},
	pages = {31-38},
	numpages = {8},
	url = {http://www.ijcaonline.org/archives/volume170/number5/28068-2017914844},
	doi = {10.5120/ijca2017914844},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

The use of Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. Therefore, an improved Frame Level Redundancy (FLR) algorithm that uses Cyclic Redundancy Check (CRC) as an error detection technique for configuration memory scrubbing, is developed as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.

References

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Keywords

FPGA, SRAM, Scrubbing, FLR, SEU, configuration memory, logic bit(s).