Call for Paper - November 2023 Edition
IJCA solicits original research papers for the November 2023 Edition. Last date of manuscript submission is October 20, 2023. Read More

A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Alireza Azimian, Ali Kargaran Dehkordi, Mohammad Tehrani

Alireza Azimian, Ali Kargaran Dehkordi and Mohammad Tehrani. A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology. International Journal of Computer Applications 172(6):1-4, August 2017. BibTeX

	author = {Alireza Azimian and Ali Kargaran Dehkordi and Mohammad Tehrani},
	title = {A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology},
	journal = {International Journal of Computer Applications},
	issue_date = {August 2017},
	volume = {172},
	number = {6},
	month = {Aug},
	year = {2017},
	issn = {0975-8887},
	pages = {1-4},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2017915156},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Recently, parallel computing has been considered increasingly and many researchers have focused on this topic in order to enhance their designs, especially speed parameter to reach lower delay in computational operations. Among the methods which use parallel computing, systolic arrays have attracted researcher’s attention because of its unique characteristics. Systolic arrays are arrays of processors which are connected to a small number of nearest neighbors in a mesh-like topology. Processors perform a sequence of operations on data that flows between them. Generally the operations will be the same in each processor, with each processor performing an operation (or small number of operations) on a data item and them passing it on to its neighbor. Systolic arrays are often using for specific operations, such as "multiply and accumulate", to perform massively parallel integration, convolution, correlation, matrix multiplication or data sorting tasks. On the other hand, silicon limitations for transistors fabrication in future causes a need to substitute this technology by an appropriate ones that among them carbon nanotube (CNT) technology has the most probability. In this paper we conducted a survey on using systolic array in multiply and accumulate operations by a VLSI circuit based on CNT technology.


  1. Kung, H. T. and Leiserson, C. E. ”Systolic arrays for VLSI”, in:Introduction to VLSI Systems, C. A. Mead and L. A. Conway, Chapter 8.3, Addison-Wesley, 1980.
  2. Lin, S., Kim, Y.B., and Lombardi, F. (2009), ‘A Novel CNTFET based Ternary Logic Gate Design’, in Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems 2009, Cancun, Mexico, 2–5 August, pp. 435–438.
  3. Y.B. Kim, Challenges for nanoscale MOSFETs and emerging nanoelectronics, Trans. Electr. Electron. Mater. 11 (3) (2010) 93–105.
  4. Keikha, A., Dadkhah, C., Tehrani, M., & Navi, K. (2011). A novel design of a random generator circuit in QCA. International Journal of Computer Applications, 35(1).
  5. Navi, K., Tehrani, M. A., & Khatami, M. (2012). Well-polarized quantum-dot cellular automata inverters. International Journal of Computer Applications, 58(20).
  6. M.H. Moaiyeri, R. Faghih Mirzaee, A. Doostaregan, K. Navi, O. Hashemipour, A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits, IET Comput. Digit. Tech. 7 (4) (2013) 167– 181.
  7. M.A. Tehrani, F. Safaei, M.H. Moaiyeri, K. Navi, Design and implementation of multi-stage interconnection networks using quantum-dot cellular automata, Microelectron. J. 42 (6) (2011) 913–922.
  8. M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology, IET Circuits Devices Syst. 5 (4) (2011) 285–296.
  9. H. Cho, and E. E. Swartzlander, Adder designs and analyses for quantum-dot cellular automata, IEEE Trans. Nanotechnol. 6 (2013) 374–383.
  10. A. S. Shamsabadi, B. S. Ghahfarokhi, K. Zamanifar and N. Movahedinia, Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study, J. Syst. Architect. 55 (2009) 180–187.
  11. J. Lee, J. H. Lee, I. Y. Chung and C. J. Kim, Comparative study on energy-efficiencies of single-electron transistor-based binary full adders including nonideal effects, IEEE Trans. Nanotechnol. 10 (2011) 1180–1190.
  12. W. Wei, J. Han and F. Lombardi, A hybrid memory cell using single-electron transfer, IEEE Int. Symp. Nanoscale Architectures, San Diego, CA, 8–9 June 2011, pp. 17–23.
  13. V. Srinivasan, R. V. Venkatraman and K. K. Senthil Kumar, Schmitt trigger based SRAM cell for ultralow power operation-A CNFET based approach, Procedia Eng. 64 (2013) 115–124.
  14. C. Vudadha, P. S. Phaneendra, V. Sreehari and M. B. Srinivas, CNFET based ternary magnitude comparator, IEEE Int. Symp. Communications and Information Technologies (ISCIT), Gold Coast, Queensland, Australia, 2–5 October 2012, pp. 942–946.
  15. Safaei, F., Moaiyeri, M. H., & Tehrani, M. A. (2011, February). Design and evaluating carbon nanotube interconnects for a generic delta MIN. In Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on (pp. 488-492). IEEE.


Systolic Array; Parallel, CNT, Matrix Multiplication, CMOS, Cell.