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A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Alireza Azimian, Ali Kargaran Dehkordi, Mohammad Tehrani
10.5120/ijca2017915156

Alireza Azimian, Ali Kargaran Dehkordi and Mohammad Tehrani. A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology. International Journal of Computer Applications 172(6):1-4, August 2017. BibTeX

@article{10.5120/ijca2017915156,
	author = {Alireza Azimian and Ali Kargaran Dehkordi and Mohammad Tehrani},
	title = {A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology},
	journal = {International Journal of Computer Applications},
	issue_date = {August 2017},
	volume = {172},
	number = {6},
	month = {Aug},
	year = {2017},
	issn = {0975-8887},
	pages = {1-4},
	numpages = {4},
	url = {http://www.ijcaonline.org/archives/volume172/number6/28252-2017915156},
	doi = {10.5120/ijca2017915156},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Recently, parallel computing has been considered increasingly and many researchers have focused on this topic in order to enhance their designs, especially speed parameter to reach lower delay in computational operations. Among the methods which use parallel computing, systolic arrays have attracted researcher’s attention because of its unique characteristics. Systolic arrays are arrays of processors which are connected to a small number of nearest neighbors in a mesh-like topology. Processors perform a sequence of operations on data that flows between them. Generally the operations will be the same in each processor, with each processor performing an operation (or small number of operations) on a data item and them passing it on to its neighbor. Systolic arrays are often using for specific operations, such as "multiply and accumulate", to perform massively parallel integration, convolution, correlation, matrix multiplication or data sorting tasks. On the other hand, silicon limitations for transistors fabrication in future causes a need to substitute this technology by an appropriate ones that among them carbon nanotube (CNT) technology has the most probability. In this paper we conducted a survey on using systolic array in multiply and accumulate operations by a VLSI circuit based on CNT technology.

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Keywords

Systolic Array; Parallel, CNT, Matrix Multiplication, CMOS, Cell.