Design convergence of System on Chips has become a major problem to solve in semiconductor industry. The advent of deep sub-micron nanometer scale transistor design, fabrication technologies and accompanying scale in design sizes have posed a major challenge regarding their implementation. For many years Electronic design automation companies have been an active partner of the design and semiconductor Fab ecosystem and have been devising new ways in methodologies and automation to solve multiple challenges the semiconductor design has been facing since its inception. Today’s complex designs and their blocks need innovative and out of the box approach in solving the convergence problem in terms of timing, power and area and additionally the runtime as well since the scale of designs is also increasing along with the complexity. Through this paper, we are going to look at the background and motivation of doing many of these shift left strategies that the design tool vendors have deployed over the years to solve the design convergence problem. After going through this paper that covers multiple aspects of the physical implementation and signoff process, the reader would get a better appreciation of why the tools are having converged methodologies and would develop a better sense of appreciation towards the software tools and its various artifacts and flows

ASIC SOC VLSI CMOS integrated circuits Moore’s law Electronic design automation physical design timing STA Quality of results