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Reseach Article

Design of the H264 application and Implementation on Heterogeneous Architectures

by Chahrazed Adda, Abou Elhassen Benyamina
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 180 - Number 7
Year of Publication: 2017
Authors: Chahrazed Adda, Abou Elhassen Benyamina
10.5120/ijca2017916056

Chahrazed Adda, Abou Elhassen Benyamina . Design of the H264 application and Implementation on Heterogeneous Architectures. International Journal of Computer Applications. 180, 7 ( Dec 2017), 23-31. DOI=10.5120/ijca2017916056

@article{ 10.5120/ijca2017916056,
author = { Chahrazed Adda, Abou Elhassen Benyamina },
title = { Design of the H264 application and Implementation on Heterogeneous Architectures },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2017 },
volume = { 180 },
number = { 7 },
month = { Dec },
year = { 2017 },
issn = { 0975-8887 },
pages = { 23-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume180/number7/28812-2017916056/ },
doi = { 10.5120/ijca2017916056 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:00:00.301513+05:30
%A Chahrazed Adda
%A Abou Elhassen Benyamina
%T Design of the H264 application and Implementation on Heterogeneous Architectures
%J International Journal of Computer Applications
%@ 0975-8887
%V 180
%N 7
%P 23-31
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multimedia applications are present in most mobile hand-held devices.H.264 is an emerging video coding standard, which aims at compressing high-quality video contents at low-bit rates. While the new encoding and decoding processes are similar to many previous standards, the new standard includes a number of new features and thus requires much more computation than most existing standards do. The complexity of H.264 standard poses a large amount of challenges to implementing the encoder/decoder in real-time requiring large amount of processing resources. This paper presents the design and analysis of the H.264 decoder implemented on a heterogeneous architecture (multi-CPUs/multi-GPUs). A model-driven approach is adopted by using the standard MARTE profile of UML. Our approach is based on hybrid partitioning that combines both functional and data partitioning which is applied to find the most suitable processors (CPU or GPU) regarding the execution time. We claim that our approach allows giving a better performance, which is crucial when implemented in modern complex systems.

References
  1. C. Nvidia. Compute unified device architecture programming guide.
  2. K. Corporation. The OpenCL Language. www.khronos.org/opencl, 2011.
  3. AISO/IEC. International standard. Part 10: Advanced video coding,
  4. JCT-VC. High efficiency video coding (HEVC) text specification draft 8. 10th Meeting: Stockholm, SE, 1120 July2012.
  5. C. S. Kannangara and I. E. G. Richardson and M. Bystrom and J. Solera and Y. Zhao and A. Maclennan Complexity reduction of H.264 using Lagrange Optimization Methods. IEE VIE 2005, Glasgow, UK, 2005.
  6. A. Gurhanli and S. Hung. Coarse grain parallelization of h.264 video decoder and memory bottleneck in multi-core architectures. International Journal of Computer Theory and Engineering vol. 3, no. 3, pages 375–381, 2011.
  7. K. Nishihara, A. Hatabu, and T. Moriyoshi. Parallelization of h.264 video decoder for embedded multicore processor. ICME, pages 329–332, 2008.
  8. A. Azevedo, C. Meenderinck, B. Juurlink, A. Terechko, J. Hooger-brugge, M. Alvarez, and A. Ramirez. Parallel h.264 decoding on an embedded multicore processor. HiPEAC, pages 404–418, 2009.
  9. J. Chong, N. Satish, B. Catanzaro, K. Ravindran, and K. Keutzer. Efficient parallelization of h.264 decoding with macro block level scheduling. ICME, pages 1874–1877, 2007.
  10. E. Van Der Tol, E. Jaspers, and R. Gelderblom. Mapping of h.264 decoding on a multiprocessor architecture. Image and Video Communications and Processing, pages 707–718, 2003.
  11. M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro. H.264/avc baseline profile decoder complexity analysis. IEEE Trans. Circuits Syst. Video Techn., 13(7):704–716, 2003.
  12. K. Sihn, H. Baik, J. Kim, S. Bae, and H. Song. Novel approaches to parallel h.264 decoder on symmetric multicore systems. Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 09, pages 2017–2020, Washington, DC, USA, 2009. IEEE Computer Society.
  13. Elias Baaklini and all, H.264 Parallel Optimization on Graphics Processors, MMEDIA 2013 : The Fifth International Conferences on Advances in Multimedia
  14. OMG, “MARTE Web Site,” 2009, www.omgmarte.org.
  15. R. Ubal, B. Jang, P. Mistry, D. Schaa, and D. Kaeli. Multi2Sim: A Simulation Framework for CPU-GPU Computing. Proc. of the 21st International Conference on Parallel Architectures and Compilation Techniques, Sep., 2012.
  16. R. Bonamy Modélisation, exploration et estimation de la consummation pour les architectures hetéerogénes reconfigurables dynamiquement HAL Id: tel-00931849 https://tel.archives-ouvertes.fr/tel-00931849v2Submitted on 17 May 2014.
  17. FFmpeg project. http://www.ffmpeg.org/.
  18. K. Suhring. H.264 reference software. http://bs.hhi.de/ suehring/tml/.
  19. TarunIyer (30 April 2013). "AMD Unveils its Heterogeneous Uniform Memory Access (hUMA) Technology". Tom's Hardware.
  20. George Kyriazis (30 August 2012). Heterogeneous System Architecture: A Technical Review (PDF) (Report). AMD.
  21. R. Ubal, B. Jang, P. Mistry, D. Schaa, and D. Kaeli. Multi2Sim: A Simulation Framework for CPU-GPU Computing. Proc. of the 21st International Conference on Parallel Architectures and Compilation Techniques, Sep., 2012.
  22. Wiegand (Ed.), T, “ Draft ITU-T Recommendation H.264/AVC and Draft ISO/IEC 14496-10 AVC”, Joint Video Team of ISO/IEC JTC1/SC29/WG11 &ITU-T SG16/Q.6 Doc. JVT-G050, Mar.
  23. Richardson, I.E.G.: Video Codec Design: Developing Image and Video Compression Systems. John Wiley and Sons (2002).
  24. Flierl, M., Girod, B.: Generalized B Pictures and the Draft H. 264/AVC Video-Compression Standard. IEEE Transactions on Circuits and Systems for Video Technology 13(7), 587–597(2003).
  25. Soon-kak Kwon, A. Tamhankar, K.R. Rao, “Overview of H.264/AVC / MPEG-4 Part 10”, Journal of Visual Communication and Image Representation, Vol. 17, No 2 , pp 186–216, Apr. 2006.
  26. Kessentini A., Kaaniche B., Werda I., Samet A., Masmoudi N., “Low complexity intra 16x16 prediction for H.264/AVC” International Conference on Embedded Systems & Critical Applications ICESCA,2008, Tunisia.
  27. Werda I., Chaouch H, Samet A, Ben Ayed M-A, Masmoudi N., “Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder”, The International Arab Journal of Information Technology, Vol. 7, No. 1, January 2010.
  28. Damak T., Werda I., Masmoudi N., Bilavarn S., “Fast prototyping H.264 deblocking filter using ESL Tools”, 2011 8th International Multi-Conference on Systems, Signals &Devices,SSD.
  29. AMD Opteron Processor Family. http://www.amd.com/.
  30. AMD Evergreen Family Instruction Set Arch. (vl.Od).
  31. http://developer.amd.com/sdks/amdappsdk/documentation/.
  32. Intel Core Processor Family. http://www.intel.com
Index Terms

Computer Science
Information Sciences

Keywords

General-Purpose Graphics Processing Unit (GPGPU) Multimedia H.264/AVC decoder Parallel Processing Functional Partitioning Data Partitioning.