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Design of IIR Systolic Array Architecture by using Linear Mapping Technique

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2019
Authors:
Manoj Kumar
10.5120/ijca2019918463

Manoj Kumar. Design of IIR Systolic Array Architecture by using Linear Mapping Technique. International Journal of Computer Applications 182(39):14-19, February 2019. BibTeX

@article{10.5120/ijca2019918463,
	author = {Manoj Kumar},
	title = {Design of IIR Systolic Array Architecture by using Linear Mapping Technique},
	journal = {International Journal of Computer Applications},
	issue_date = {February 2019},
	volume = {182},
	number = {39},
	month = {Feb},
	year = {2019},
	issn = {0975-8887},
	pages = {14-19},
	numpages = {6},
	url = {http://www.ijcaonline.org/archives/volume182/number39/30349-2019918463},
	doi = {10.5120/ijca2019918463},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Design of IIR (infinite impulse response) systolic array architecture by using linear mapping technique is proposed in this paper. Systolic array architecture maps high level computations into hardware structures. In a systolic array, all the processing elements (PEs) are uniform and fully pipelined. On regular dependence graph, systolic architectures are designed by using linear mapping techniques. IIR filters are used in digital signal and image processing applications. IIR filters are recursive filters. IIR filters have high selectivity and less number of coefficients than the FIR (finite impulse response) filters. Various IIR systolic arrays architectures such as design B1, design B2, and design F is proposed in this paper. By selecting the projection vector, processor vector and scheduling vector these designs are derived.

References

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Keywords

Systolic array, DG, PEs, FIR, IIR, DSP