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Design of IIR Systolic Array Architecture by using Linear Mapping Technique

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2019
Manoj Kumar

Manoj Kumar. Design of IIR Systolic Array Architecture by using Linear Mapping Technique. International Journal of Computer Applications 182(39):14-19, February 2019. BibTeX

	author = {Manoj Kumar},
	title = {Design of IIR Systolic Array Architecture by using Linear Mapping Technique},
	journal = {International Journal of Computer Applications},
	issue_date = {February 2019},
	volume = {182},
	number = {39},
	month = {Feb},
	year = {2019},
	issn = {0975-8887},
	pages = {14-19},
	numpages = {6},
	url = {},
	doi = {10.5120/ijca2019918463},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Design of IIR (infinite impulse response) systolic array architecture by using linear mapping technique is proposed in this paper. Systolic array architecture maps high level computations into hardware structures. In a systolic array, all the processing elements (PEs) are uniform and fully pipelined. On regular dependence graph, systolic architectures are designed by using linear mapping techniques. IIR filters are used in digital signal and image processing applications. IIR filters are recursive filters. IIR filters have high selectivity and less number of coefficients than the FIR (finite impulse response) filters. Various IIR systolic arrays architectures such as design B1, design B2, and design F is proposed in this paper. By selecting the projection vector, processor vector and scheduling vector these designs are derived.


  1. H.T.Kung and C.E.Leiserson, “Systolic arrays (for VLSI),” in Sparse Matrix Symposium, SIAM, pp.256-282, 1978.
  2. H.T.Kung,” Why systolic architectures? IEEE Commuters Magazine, vol.15, pp.37-45, Jan. 1982.
  3. Dimitris G. Manolakis,John G. Proakis,:Digital Signal Processing: Principles, Algorithm, and Applications”, Macmillan Publishing Company, 1992.
  4. G.Ramana Murthy,C.Senthilpari,P.velrajkumar, Lim Tien sze,”Design of Low Power and High Speed Digital IIR Filter in 45nm with Optimized CSA for Digital Signal Processing Applications”,International Journal of Electrical and Computer Engineering,vol.7,no.4,2013.
  5. S.Y.Kung, VLSI Array Processors. Prentice Hall, 1998.
  6. H. V. Jagadish, S. K.Rao, and T. Kailath, “Array architecture for iterative algorithm,”Proc. IEEE, vol.75, no.9, pp.1304-1321, Sept.1987.
  7. K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
  8. A.Madanayake,Randeel Wimalagunarathne, Donald G. Dansereau and Len T.Bruton ,”Design and FPGA-implementation of 1st-order 4D IIR frequency-hyperplane digital filters, in Circuits and systems(MWSCAS),2011 IEEE 54th International Midwest Symposium on,pp.1-4,2011.
  9. D.Dansereau and L.Bruton,” A 4D freq*uency –planar IIR filter and its application to light filed processing”, ISCAS 2003, vol.4,pp.476-479,2003.
  10. Siji P.V and Manju Manuel,”2D IIR Spatially Bandpass Beam Filter-A Multiplierless Realization” International Advanced Research Journal in Science, Engineering and Technology, vol.2, no.10, 2015.
  11. Sagara K.S and Ravi L. S ,”IIR filter design using CSA for DSP applications “International Journal for Research in Applied Science & Engineering Technology(IJRASET),vol.3,no.VI,2015.


Systolic array, DG, PEs, FIR, IIR, DSP