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21 September 2026
Reseach Article

Optimized 4:2 Compressor based Approximate Multiplier for Low Power Digital Signal Processing

by K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S.
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 187 - Number 144
Year of Publication: 2026
Authors: K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S.
10.5120/ijca2bef88369267

K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S. . Optimized 4:2 Compressor based Approximate Multiplier for Low Power Digital Signal Processing. International Journal of Computer Applications. 187, 144 ( Sep 2026), 7-18. DOI=10.5120/ijca2bef88369267

@article{ 10.5120/ijca2bef88369267,
author = { K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S. },
title = { Optimized 4:2 Compressor based Approximate Multiplier for Low Power Digital Signal Processing },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2026 },
volume = { 187 },
number = { 144 },
month = { Sep },
year = { 2026 },
issn = { 0975-8887 },
pages = { 7-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume187/number144/optimized-42-compressor-based-approximate-multiplier-for-low-power-digital-signal-processing/ },
doi = { 10.5120/ijca2bef88369267 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2026-09-19T02:57:40.838711+05:30
%A K. Ezhilarasan
%A Kaveri S.
%A K. Bhavya Sree
%A Shreyas M.
%A Vidyashree K.S.
%T Optimized 4:2 Compressor based Approximate Multiplier for Low Power Digital Signal Processing
%J International Journal of Computer Applications
%@ 0975-8887
%V 187
%N 144
%P 7-18
%D 2026
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In many digital signal processing systems, multiplication is the workhorse and also the biggest drain on power, area, and latency. This paper introduces an elegant compressor an enhanced multiplier built around approximate 4:2 compressors that trims energy and hardware cost while preserving the fidelity that matters. The design uses a hybrid compression strategy; the most significant bits are handled by exact 4:2 compressors to protect numerical accuracy where it counts, while the least significant bits are handled by lightweight approximate 4:2 compressors. By selectivity relaxing correctness only where the impact on the overall result is small, the architecture dramatically reduces switching activity, shortens critical – path delay, and shrink resource usage. Partial products are aggregated in a structured compression tree and finished off with a fast final adder to produce the product. To quantify trade-offs, the design is evaluated on power, propagation delay, area, and accuracy metrics (Mean Error Distance and Error Rate). Results show notable improvements in power–delay product and area efficiency compared with exact multipliers, while introducing only modest, generally acceptable errors. The result is a compelling multiplier option for DSP contexts that can tolerate slight inaccuracies in exchange for lower power and smaller silicon footprint.

References
  1. M. Rashidi, H. Saeidi, and A. Afzali-Kusha, “Area-efficient and high-performance approximate multiplier based on approximate 4:2 compressor, “Integrated, the VLSI Journal, vol. 96, pp. 1-10, 2026.
  2. B. Rashidi, “Area-efficient and high-performance approximate multiplier based on approximate 4:2 compressors,” Integration, the VLSI Journal, vol. 109, pp. 102693, 2025.
  3. A. Chakraborty, S. DasandP.Banerjee, “Optimized approximate compressor architectures for Dadda multipliers,” Microelectronics Journal, vol. 146, pp. 106018, 2025.
  4. P. Jaswal, L. Krishna and B. Srinivasu, “Low-power approximate multipliers for neural network applications,” IEEE Access, vol. 13, pp. 32112-32122, 2025.
  5. L. Krishna, S.Bodapati and S. Veeramachaneni, “Approximate signed multipliers for image processing system,” Integration, the VLSI Journal, vol. 110, pp. 115-124,2025.
  6. R. Singh and P. Sharma, “Low-power approximate 4:2 compressor designed for circuits,” IEEE Access, vol. 13, pp. 45876-45886,2025.
  7. S. Patel and R. Shah, “Optimized compressor – based multiplier architectures for DSP applications,” Microelectronics Journal, vol. 147, pp. 106095,2025.
  8. L. Li Y. Jiang and X. Wang, “Energy-efficient approximate multiplier using compressors circuits,” IEEE Access, vol. 12,pp. 24810-24820,20204.
  9. Z. Zuhair, A. Mahmood and M. Tariq, “Design of optimized approximate 4:2 compressors for multiplier circuits,” Integration, the VLSI Journal, vol. 97, pp. 215-224, 2024.
  10. S. Vakili and M. Taheri, “Compact approximate compressors for efficient Dadda multipliers,” Microelectronics Journal, vol. 140, pp. 105831, 2024
  11. A. Bhandari and P. Kumar, “Analysis of approximate compressor architectures for arithmetic circuits,” IEEE Access, vol. 12, pp. 32517-32527, 2024.
  12. Z. Ren, X. Liu and J. Chen, “Approximate multipliers for deep neural network accelerators, “IEEE Transaction Circuits and Systems, vol. 71, no. 2, pp. 755-768,2024.
  13. P. Gupta and R. Mehta, “Low-power approximate compressor circuits for multimedia systems,” Microelectronics Journal, vol. 141, pp. 105905, 2024.
  14. Y. Zhang and H. Yang, “Probability-based approximate compressor architecture for arithmetic circuits,” IEEE Access, vol. 12, pp. 58711-58720, 2024.
  15. H. Yang and X. Li, “Optimized approximate multiplier architectures for VLSI systems,” Integrated, the VLSI Journal, vol. 98, pp. 301-309, 2024.
  16. A. Guturuand S. Gupta, “Compressor selection techniques for efficient multiplier design,” IEEE Access, vol. 12, pp. 91820-91830, 2024.
  17. A. Rehman and M. Shafique, “Architecture for approximate multipliers with low error and high efficiency,” IEEE Access, vol. 11, pp. 22418-22429, 2023.
  18. Y. Jiang, J. Han and F. Lombardi, “Low-power approximate compressors for arithmetic circuits,” IEEE Transactions on Circuits and Systems 1, vol. 70, no. 3, pp. 1105-1115, 2023
  19. P. Gupta and R. Kumar, “Low-power approximate multiplier design for signal processing applications,” Microelectronics Journal, vol. 135, pp. 105622,2023.
  20. J. ParkandH.Kim, “Approximate multiplier architecture for image processing system,” IEEE Access, vol. 11, pp, 76321-76330, 2023.
  21. A. Ali, M. Ahmed and S. Khan, “Area-efficient approximate multipliers for VLSI applications,” Integration, the VLSI Journal, vol. 92, pp. 112-121, 2023.
  22. S. Singh and R. Patel, “Compressor-based approximate multiplier design for DSP applications,” International Journal of Electronics, vol. 110, no. 7, pp. 1185-1198, 2023
  23. M. Akbari, A. Eslami and M. Pedram, “Approximate multipliers for energy-efficient digital signal processing,” IEEE Access, vol. 10, pp. 12567-12578, 2022.
  24. J. Han and M. Orshansky, “Approximate computing: An emerging paradigm for energy-efficient design,” IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 1, pp. 1-15, 2022.
  25. A. Momeni, J. Han, P. MontuschiandF. Lombardi, “Design and analysis of approximate compressors for multiplication, “IEEE Transactions Compressors, vol. 71, no. 3, pp. 621-633, 2022.
  26. H. Kim and S. Lee, “High-performance approximate multiplier design for DSP applications,” Microelectronics Journal, vol. 122, pp. 105432, 2022.
  27. Y. Jiang, L. Liu and J. Han, “Approximate arithmetic circuits: A survey, characterization and recent applications,” IEEE Design & Test, vol. 39, no. 2, pp. 8-21, 2022.
  28. V. Lakshmi, K. Ezhilarasan and S. N, “FPGA Implementation of efficient and low power test pattern generator,” 2022 2nd Asian conference on innovation in technology (ASIANCON), Ravet, India, 2022, pp. 1-5, doi: 10.1109/ASIANCON55314. 2022. 9908689.
  29. Bhavyashree H, Dr. K Ezhilarasan, High-speed carry look-ahead decimal adder design: a Verilog and FPGA- Based implementation and comparative study with hybrid and majority-logic decimal adders, computer science journal, volume 16, issue 9 page no: 21-38, 2026. Doi: 10.14118.CSJ.2026.V1619.003.
  30. Shylaja V, Dr. K Ezhilarasan, Insights of performance enhancement techniques on high-speed computation multiple 4-bit ALU, page no: 427-444. Doi: 20.18001. Jot.2023.V11111.23.2944.
Index Terms

Computer Science
Information Sciences

Keywords

Approximate Computing 4:2 Compressor Approximate Multiplier Hybrid Compression Low Power Design Digital Signal Processing (DSP) Partial Product Reduction Error Tolerant Systems Power-Delay Product (PDP) VLSI Architecture