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Low-Power 200 MS/s 4-bit Flash ADC with Optimized Dynamic Comparator in 90 NM CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 187 - Number 8 |
| Year of Publication: 2025 |
| Authors: Reena G., Nagesh Ch. |
10.5120/ijca2025924997
|
Reena G., Nagesh Ch. . Low-Power 200 MS/s 4-bit Flash ADC with Optimized Dynamic Comparator in 90 NM CMOS Technology. International Journal of Computer Applications. 187, 8 ( May 2025), 1-8. DOI=10.5120/ijca2025924997
Abstract
In this paper, a low-power flash ADC has been designed and implemented in 90 nm CMOS technology with a supply voltage of 0.8 V. In the proposed flash ADC, a low-power double-tail dynamic comparator (DTDC) is utilized. With the addition of two PMOS transistors MR4 and MR5 to the DTDC’s controlled reset phase, the internal nodes of the reset phase gradually discharge lowering the DTDC’s power consumption, which in turn reduces the flash ADC architecture’s overall power consumption. The important parameters have been studied through the simulation results in order to analyze the performance of flash ADC. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.28/-0.37 LSB and +0.24/-0.43 LSB, respectively. With a 1.36 MHz input signal, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 24.4 dB and 28.75 dB, respectively. The effective number of bits (ENOB) is 3.82 bits at 200 MS/s after the post layout simulation. It is found that the total footprint of the ADC architecture is 90*95 μm*μm. The overall power consumption is reduced to 45.3 % compared to existing work
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