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Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 22 - Number 3 |
| Year of Publication: 2011 |
| Authors: Dinesh Sharma, Rajesh Mehra |
10.5120/2565-3526
|
Dinesh Sharma, Rajesh Mehra . Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology. International Journal of Computer Applications. 22, 3 ( May 2011), 13-18. DOI=10.5120/2565-3526
Abstract
This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold voltage (Vth) are scaled for low voltage applications in deep submicron (DSM) region. The proposed buffer has been designed and simulated using Tanner SPICE tool in 70 nm VLSI technology node. The results show that modified taper buffer design provides 15% reduction in power dissipation at same value of propagation delay when compared with conventional design.
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