Call for Paper - June 2018 Edition
IJCA solicits original research papers for the June 2018 Edition. Last date of manuscript submission is May 21, 2018. Read More

Built-In Self-Repair for multiple RAMs with different Redundancies in a SOC

International Journal of Computer Applications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
Shekar Babu M
Sumanth Kumar Reddy
S V V Sateesh

Shekar Babu M, Sumanth Kumar Reddy and S V V Sateesh. Article: Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC. International Journal of Computer Applications 24(8):26–29, June 2011. Full text available. BibTeX

	author = {Shekar Babu M and Sumanth Kumar Reddy and S V V Sateesh},
	title = {Article: Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {24},
	number = {8},
	pages = {26--29},
	month = {June},
	note = {Full text available}


As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.


  • R. Rajsuman, “Design and test of large embedded memories: an overview,” IEEE, vol. 18, no. 3, May 2001.
  • Yu-Ming Jia, Quan-Lin Rao and Chun He “A Memory Built-In Self-Test Architecture for memories different in size,” IEEE 2009.
  • Kiamal Pekmestzi, Nicholas Axelos, Isidoros Sideris and Nicolaos Moshopoulos, “A BISR Architecture for Embedded Memories,” 14th IEEE International On-Line Testing Symposium 2008.
  • Muhammad Tauseef Rab, Asad Amin Bawa, and Nur A. Touba, “Improving Memory Repair by Selective Row Partitioning,” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009.
  • Jin-Fu Li, Rei-Fu Huang, Jen-Chieh Yeh and Cheng-Wen Wu, “A Built-In Self-Repair Design for RAMs With 2-D Redundancy” ieee transactions on very large scale integration (vlsi) systems, June 2005.
  • Chun-Lin Yang, Shyue-Kung Lu, and Han-Wen Lin, “Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy” 2006.
  • Jin-Fu Li, Member, IEEE, Tsu-Wei Tseng and Chih-Chiang Hsu, “ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs,” IEEE transactions on very large scale integration (vlsi) systems, JUNE 2010.
  • C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: An infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. Very Large Scale Integr (VLSI) Syst., vol. 15, no. 10, pp. 1135–1143, Oct. 2007.
  • T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, A. Pao, K. Chiu, and E. Chen, “A built-in self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, CA, May 2007, pp. 355–360.
  • A. Benso, S. Chiusano, G. D. Natale, and P. Prinetto, “An on-line BIST RAM architecture with self-repair capabilities,” IEEE Trans. Reliab. vol. 51, no. 1, pp. 123–128, Mar. 2002.
  • C.-D. Huang, T.-W. Tseng, and J.-F. Li, “An infrastructure IP for repairing multiple RAMs in SOCs,” in Proc. IEEE Int. Symp. VLSI Des., Autom., Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 163–166.
  • J.-F. Li and C.-W. Wu, “Memory fault diagnosis by syndrome compression,” in Proc. Conf. Des., Autom., Test Eur. (DATE),Munich, Germany, Mar. 2001, pp. 97–101.
  • T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs,” in Proc. Int. Test Conf. (ITC), Santa Clara, CA, Oct. 2006,pp. 1–8, Paper 30.2.
  • M. Nicolaidis, N. Achouri, and S. Boutobza, “Optimal reconfiguration functions for column or data-bit built-in self-repair,” in Proc. Conf. Des., Autom., Test Eur. (DATE), Munich, Germany, Mar. 2003, pp. 590–595.