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Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 25 - Number 7 |
| Year of Publication: 2011 |
| Authors: Narendra Singh Pal, Harjit Pal Singh, R.K.Sarin, Sarabjeet Singh |
10.5120/3043-4131
|
Narendra Singh Pal, Harjit Pal Singh, R.K.Sarin, Sarabjeet Singh . Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm. International Journal of Computer Applications. 25, 7 ( July 2011), 26-32. DOI=10.5120/3043-4131
Abstract
This paper describes the implementation of highly efficient multiplierless serial and parallel distributed arithmetic algorithm for FIR filters. Distributed Arithmetic (DA) had been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the bit-serial and bit-parallel DA technique for FIR filter design is analyzed and the results are compared to the conventional FIR filter design techniques. The proposed algorithm has been synthesized with Xilinx ISE 10.1i and implemented as a target device of Spartan3E FPGA.
References
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