The week's pick
Reseach Article
Efficient Crosstalk Reduction Technique for Data Bus
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 28 - Number 11 |
| Year of Publication: 2011 |
| Authors: A.Sathish, Dr. M. Madhavi Latha, Dr. K. Lal Kishore |
10.5120/3520-4715
|
A.Sathish, Dr. M. Madhavi Latha, Dr. K. Lal Kishore . Efficient Crosstalk Reduction Technique for Data Bus. International Journal of Computer Applications. 28, 11 ( August 2011), 37-40. DOI=10.5120/3520-4715
Abstract
Crosstalk has become the great challenge to the design community in Deep-submicron (DSM) and Very Deep-submicron (VDSM) technologies. As the portion of silicon area for interconnects and buses is dominating, crosstalk effect also dominates in deciding the reliability and performance of the SoCs and many types of processors. These interconnect and buses are prone to errors due to crosstalk. The major part of the crosstalk is due to coupling transitions occurring on the data bus and interconnects when signals are transmitted. One of the favorable techniques to reduce the crosstalk is to reduce the coupling transitions. Bus encoding technique is the promising method to reduce the crosstalk. Hence an efficient Crosstalk reduction data bus encoding scheme is proposed which can reduce the 6C, 5C and 4C crosstalk for 64-bit data bus around 88%, 68% and 24% respectively, for 32-bit data bus around 89%, 74% and 32% respectively and 16-bit data bus by 93%, 71% and 19% respectively.
References
- M.R.Stan and W.P.Burleson, “Bus-Invert coding for low-power I/O”.IEEE Trans. On VLSI, March 1995. vol. 3, pp.49-58.
- P.P. Sotiriadis, A. Chandrakasan, “Low power bus coding techniques considering inter-wire capacitances,” Custom Integrated Circuits Conference, 2000.
- T.Sakurai “Closed-form expressions for Interconnect Delay, Coupling and Crosstalk in VLSI’s” IEEE Transactions on Electron Devices, Jan 1993, pp.118-124.C.
- Duan, A. Tirumala, and S. P. Khatri, ”Analysis and Avoidance of Cross-talk in On-Chip Buses,” Hot Interconnects, pp. 133-138, August 2001.
- J.Ma and L.He, “Formulae and application of interconnect estimation considering shield insertion and net ordering” in Proc. ICCAD, 2001, pp. 327-332.
- L. Macchiarulo, E. Macii, M. Poncino, “Wire placement for crosstalk energy minimization in address buses,” Proceedings Design, Automation and Test in Europe Conference and Exhibition, 4-8, pages:158 – 162, March 2002.
- M.Madhu, V.Srinivas Murty, V.Kamakoti, “Dynamic coding Technique for Low-Power data bus” Proc. IEEE computer Society Annual Symposium on VLSI (ISVLSI’03).
- Peter Petrov, Alex Orailoglu, “Low-Power instruction Bus Encoding for Embedded Processors”, IEEE Trans. VLSI Systems, vol. 12, No. 8 August 2004, pp. 812-826.
- NK Samala, D Radhakrishnan, B Izadi “A Novel deep submicron Bus Coding for Low Energy” In Proceedings of the International Conference on Embedded Systems and Applications, pp. 25 – 30, June 2004.
- Natesan J.; Radhakrishnan, D. “Shift invert coding (SINV) for low power VLSI” IEEE Conference on Digital System Design, pp. 190-194.
- J.V.R. Ravindra, N. Chittarvu, M.B. Srinivas, “Energy Efficient Spatial Coding Technique for Low Power VLSI Applications” Proceedings of the 6th International Workshop on System-on-Chip for Real-Time Applications, pp 201 – 204, Dec. 2006.
- Z. Khan, T. Arslan and A.T. Erdogan, “Low power system on chip bus encoding scheme with crosstalk noise reduction capability,” IEE Proceedings-Computers and Digital Techniques, Volume 153, pages:101 – 108, March 2006.
- Daniele Rossi, Andre K.Nieuwland, Steven V.E.S. van Dijk, Richard P.Kleihorst and Cecilia “Power consumption of Fault tolerant buses” IEEE transactions on very large scale integration (VLSI) systems, Vol. 16, No.5. May 2008.
- Rohit Singhal, Gwan Choi and Rabi N. Mahapatra “Data Handling Limits of On-Chip Interconnects” IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 16, No.6. June 2008.
- A.Sathish and T.Subba Rao “Bus Regrouping method to optimize Power in DSM Technology” Proc.IEEE-international Conference on Signal processing, Communications and Networking, pp.432-436, Jan, 2008.
- Katherine shu-Min Li, Chung-Len Lee, Chauchin Su and Jwu E Chen “A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus” IEEE transactions on very large scale integration (VLSI) systems, Vol. 17, No.2. February2009.
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