Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder/Subtractor and Match Logic
![]() |
10.5120/3854-5372 |
Diganta Sengupta, Mahamuda Sultana and Atal Chaudhuri. Article:Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder/Subtractor and Match Logic. International Journal of Computer Applications 31(9):30-35, October 2011. Full text available. BibTeX
@article{key:article, author = {Diganta Sengupta and Mahamuda Sultana and Atal Chaudhuri}, title = {Article:Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder/Subtractor and Match Logic}, journal = {International Journal of Computer Applications}, year = {2011}, volume = {31}, number = {9}, pages = {30-35}, month = {October}, note = {Full text available} }
Abstract
In recent years, Quantum Electronics and Reversible Logic have emerged as a major area of research having applications in low power CMOS circuits, cryptography, optical computing and nanotechnology. The fact that classical logic gates such as AND, OR, XOR etc., barring the NOT gate, cannot predict the input given the output and hence generate heat due to information loss, has given rise to the concept of reversible logic. In this paper, a new reversible 4 * 4 “SCG” gate has been proposed which is being used to realize the classical set of logic gates in the reversible domain. The most promising fact of the proposed gate is that a single SCG gate can be used to realize a reversible Full Adder/Subtractor circuit or a single bit reversible Comparator. It has been shown that the Full Adder/Subtractor and the single bit Comparator using the proposed gate is much better and optimized in terms of number of garbage outputs and the number of reversible gates used in comparison to the existing counterparts in literature. Further efficient Reversible Parallel Adder/Subtractor circuits and Match Logic have been designed using the proposed SCG gate. Also a 4-bit digital comparator has been designed by cascading a series of single bit comparators using SCG gate.
Reference
- Landauer, R., “Irreversibility and heat generation in the computing process”, IBM J. Research and Development, vol. 5 (3): pp. 183-191, 1961.
- M. P. Frank, “Introduction to reversible computing: motivation, progress and challenges”, In Proceedings of the 2nd Conference on Computing Frontiers, 2005, pp 385-390.
- Bennett, C.H., “Logical reversibility of computation”, IBM J. Research and Development, vol. 17: pp. 525-532, 1973
- Peres, A., “Reversible logic and quantum computers”, Physical Review: A, vol. 32 (6): pp. 3266-3276, 1985.
- H Thapliyal and M. Srinivas, “Novel reversible TSG gate and its application for designing carry look ahead adder and other adder architectures”, Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), 2005, pp 775-786.
- Saiful Islam M. and Md. Rafiqul Islam, “Minimization of reversible adder circuits”. Asian J. Inform. Tech., vol. 4 (12): pp. 1146-1151, 2005.
- G Schrom, “Ultra Low Power CMOS Technology”, PhD Thesis, Technischen UniversitatWien, June 1998.
- E. Knil, R. Laflamme, and G.J Milburn, “ A Scheme for Efficient Quantum Computation With Linear Optics”, Nature, pp 46-52, Jan 2001.
- M. Nielsen and I. Chaung, “Quantum Computation and Quantum Information”, Cambridge University Press, 2000.
- R.C. Merkle, “Two Types of Mechanical Reversible Logic”, Nanotechnology, vol. 4:pp. 114-131, 1993.
- Feynman, R., “Quantum mechanical computers”, Optics News, vol. 11: pp. 11-20, 1985.
- Toffoli T., Reversible Computing, Tech Memo MIT/LCS/TM-151. MIT Lab for Computer Science, 1980
- Fredkin, E. and T. Toffoli, “Conservative Logic”. Int’l J. Theoretical Physics, vol. 21: pp. 219-253, 1982.
- Md. M. H. A. Khan, “Design of Full Adder with reversible gate”, International Conference on Computer and Information Technology, 2002, pp 515-519.
- Haghparast, M. and K. Navi, “A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems”. J. Applied Sci., vol. 7 (24) pp. 3995-4000, 2007
- Haghparast M. and K. Navi, “A Novel reversible BCD adder for nanotechnology based systems”. Am. J. Applied Sci., vol. 5 (3), pp. 282-288, 2008.
- H. Thapliyal and M.B Srinivas, “A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits”, Proceedings of the 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM 2005), Tokyo, Japan, 2005.
- Lala P. K., Parkerson J. P., Chakraborty P., “Adder Designs using Reversible Logic Gates” WSEAS Transactions. on Circuits and Systems, 2010
- Islam, M.S. et a!.,"Low cost quantum realization of reversible multiplier circuit", Information technology journal,vol. 8, pp 208, 2009
- H. Md. H Babu, Md. R. Islam, S. M. A Chowdhury and A. R. Chowdhury, “Reversible Logic synthesis for Minimization of Full-Adder Circuit”, Proceedings of the EuroMicro Symposium on Digital System Design (DSD ‘03), 2003, pp 50-54.
- H. Md. H Babu, Md. R. Islam, S. M. A Chowdhury and A. R. Chowdhury, “Synthesis of Full Adder Circuit using Reversible Logic”, Proceedings 17th International Conference on VLSI Design (VLSI Design 2004), 2004, pp 757-760.
- S. Islam, Md. M Rahman, Z. Begum and Md. Z Hafiz, “Realization of a novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology”, The Int’l Arab J if Information Technology, vol. 7 (3), pp. 317-322, 2010.
- Bruce J., “Efficient Adder Circuits Based on a Conservative Reversible Logic Gates,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Pittsburg, pp. 83-88, 2002.