The week's pick
Random Articles
Reseach Article
Design of Area and Power Efficient Modified Carry Select Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 33 - Number 3 |
| Year of Publication: 2011 |
| Authors: Sarabdeep Singh, Dilip Kumar |
10.5120/3999-5666
|
Sarabdeep Singh, Dilip Kumar . Design of Area and Power Efficient Modified Carry Select Adder. International Journal of Computer Applications. 33, 3 ( November 2011), 14-18. DOI=10.5120/3999-5666
Abstract
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumption. The Modified Carry Select-Adder (MCSA) is designed for 8-bit, 16-bit, 32-bit and 64-bit and then compared with conventional CSA respective architectures. MCSA shows reduction in area and power consumption in comparison with conventional CSA with small increase in delay.
References
- Kuldeep Rawat, Tarek Darwish. and Magdy Bayoumi, “A low power and reduced area Carry Select Adder”, 45th Midwest Symposium on Circuits and Systems, vol.1, pp. 467-470,March 2002.
- O. J. Bedrij, “Carry-Select Adder”, IRE transactions on Electronics Computers, vol.EC-11, pp. 340-346, June1962.
- Youngjoon Kim and Lee-Sup Kim, “64-bit carry-select adder with reduced area”, Electronics Letters, vol.37, issue 10, pp.614-615, May 2001.
- B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, “ASIC implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research, vol.42, pp.53-58, 2010.
- J. M. Rabaey, “Digital Integrated Circuits- A Design Perspective”, New Jersey, Prentice-Hall, 2001..
- M.Moris Mano, “Digital Design”, Pearson Education, 3rd edition, 2002.
- 7 T.-Y. Chang and M.-J. Hsiao,“Carry-Select Adder using single Ripple-Carry Adder”, Electronics letters, vol.34, pp.2101-2103, October 1998.
- Youngjoon Kim and Lee-Sup Kim, “A low power carry select adder with reduced area”, IEEE International Symposium on Circuits and Systems, vol.4, pp.218-221, May 2001.
- Behnam Amelifard, Farzan Fallah and Massoud Pedram, “Closing the gap between Carry Select Adder and Ripple Carry Adder: a new class of low-power high-performance adders”, Sixth International Symposium on Quality of Electronic Design, pp.148-152. April 2005.
- Akhilesh Tyagi, “A Reduced Area Scheme for Carry-Select Adders”, IEEE International Conference on Computer design, pp.255-258, Sept 1990
- Yajuan He, Chip-Hong Chang and Jiangmin Gu, “An area efficient 64-bit square root Carry-Select Adder for low power applications”, IEEE International Symposium on Circuits and Systems,vol.4, pp.4082-4085, May 2005.
- D. J. Kinniment, “An evaluation of asynchronous addition”, IEEE transaction on very large scale integration (VLSI) systems, vol.4, pp.137-140, March 1996.
- Richard P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”, IEEE transactions on Computers, vol.c-31, pp.260-264, March 1982.
- Singh, R.P.P.; Kumar, P.; Singh, B., “Performance Analysis of Fast Adders Using VHDL”, Advances in Recent Technologies in Communication and Computing, 2009. ART Com '09. International Conference on , vol., no., pp.189-193, 27-28 Oct. 2009
- Belle W.Y.Wei and Clark D.Thompson, “Area-Time Optimal Adder Design”, IEEE transactions on Computers, vol.39, pp. 666-675, May1990.
- David Jeff Jackson and Sidney Joel Hannah, “Modelling and Comparison of Adder Designs with Verilog HDL”, 25th Southeastern Symposium on System Theory, pp.406-410, March 1993.
Index Terms
Keywords