CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter

by Ashish Raman, Vignesh.V, Deepti Kakkar
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 34 - Number 4
Year of Publication: 2011
Authors: Ashish Raman, Vignesh.V, Deepti Kakkar
10.5120/4089-5898

Ashish Raman, Vignesh.V, Deepti Kakkar . ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter. International Journal of Computer Applications. 34, 4 ( November 2011), 45-50. DOI=10.5120/4089-5898

@article{ 10.5120/4089-5898,
author = { Ashish Raman, Vignesh.V, Deepti Kakkar },
title = { ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter },
journal = { International Journal of Computer Applications },
issue_date = { November 2011 },
volume = { 34 },
number = { 4 },
month = { November },
year = { 2011 },
issn = { 0975-8887 },
pages = { 45-50 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume34/number4/4089-5898/ },
doi = { 10.5120/4089-5898 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:20:15.473648+05:30
%A Ashish Raman
%A Vignesh.V
%A Deepti Kakkar
%T ASIC Implementation of a High Speed, Low Area Reconfigurable Decimation Filter
%J International Journal of Computer Applications
%@ 0975-8887
%V 34
%N 4
%P 45-50
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Decimation filter is used to reduce the sampling rate for succeeding stages of an oversampling ADC. The speed of a successive-approximation ADC predominately depends on the decimator speed. This necessitates a need to design a high speed decimation filter to improve the overall system performance. A reconfigurable architecture is applied for the design of decimator to serve this purpose. Results show that delay of a Reconfigurable Decimator is reduced by 29.74% compared to a Normal Decimation filter. The Number of Slices and 4 Input LUTs are reduced by 6% and 7% each, which reduces the Area.

References
  1. Mohamed Ali Mahdi Eshtawie and Masuri Bin Othman, “An Algorithm proposed for FIR Filter Coefficients Representation”, International Journal of Applied mathematics and Computer Sciences, Vol 4 No. 1, 2008, pp24-pp30.
  2. E.Abu-Shama, M.B.Maaz, and M.A.Bayoumi, A fast and low power multiplier architecture. Proceedings of the 39th Midwest Symposium on Circuits and Systems (1997), pp.26–32.
  3. R. Veljanovski, J.Singh and M. Faulkner “DSP and ASIC Implementation of A Channel Filter For A 3G Utra-Tdd System” Personal, Indoor and Mobile Radio Communications. The 13th IEEE International Symposium, 2002 Vol 3, pp 1447-1451
  4. P. P. Vaidyanathan, Multirate systems and Filter Banks, Prentice Hall, Inc., 1993.
  5. A. Oppenheim; R. Schafer, Discrete-Time Signal Processing: 3rd Edition, Prentice Hall, 2009.
  6. Clive Maxfield "The design warrior's guide to FPGAs: devices, tools and flows".
Index Terms

Computer Science
Information Sciences

Keywords

oversampling successive approximation ADC reconfigurable architecture

Powered by PhDFocusTM