The week's pick
Random Articles
Reseach Article
Hardware Implementation of FFT using Vertically and Crosswise Algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 35 - Number 1 |
| Year of Publication: 2011 |
| Authors: Nidhi Mittal, Abhijeet Kumar |
10.5120/4365-6020
|
Nidhi Mittal, Abhijeet Kumar . Hardware Implementation of FFT using Vertically and Crosswise Algorithm. International Journal of Computer Applications. 35, 1 ( December 2011), 17-20. DOI=10.5120/4365-6020
Abstract
This paper is devoted for the implementation of FFT, which uses Vertical and Crosswise algorithms. Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. But the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem UrdhvaTirvagbhyam in Vedic mathematics is an efficient method of multiplication. It literally means “Vertically and crosswise”. It is based on a novel concept through which the generation of all partial products can be done and then, concurrent addition of these partial products can be done. It is one of the sutra of Vedic Mathematics equally applicable to all cases of multiplication. The conventional multiplication method requires more time & area on silicon than Vedic algorithms. In this paper the design for the architecture of FFT using Vertically and Crosswise is proposed and described using Verilog hardware description language. The code description is simulated using ModelSim SE 5.7f and synthesized using ISE Xilinx 9.2i for the FPGA device Spartan XC3S500e-fg320, Speed Grade-4. The results show how by combining these two approaches proposed design methodology is time, area and power efficient.
References
- Ashish Raman, Anvesh Kumar, R.K.Sarin, ‘‘High Speed Reconfigurable FFT Design by Vedic Mathematics’’, journal of Computer Science and Engineering, vol.1, pp 59-63 May 2010.
- Anvesh Kumar, Ashish Raman, ‘‘Small Area Reconfigurable FFT Design by Vedic Mathematics”, vol 5, IEEE pp 836-838, 2010.
- Laxman P. Thakre, Suresh Balpande,UmaehAkare, SudhairLande, ‘‘Performance evaluation and Synthesis of Multiplier Used in FFT Operation Using conventional and Vedic Algorithm”, International Conference on emerging trends in Engineering and Technology, pp 614-619, 2010.
- M.E.Paramasivam, Dr.R.S.Sabeenian, ‘‘An Efficient Bit Reduction Binary Multiplication Algorithm using Vedic Methods”, IEEE pp 25-28, 2010.
- Anvesh Kumar, Ashish Raman, ‘‘Low Power ALU Design by Ancient Mathematics”, vol 5, IEEE pp 862-865, 2010.
- SumitVaidya, Deepak Dandekar, ‘‘Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, pp 47-56 July 2010.
- Leonard Gibson Moses S, Thilagar M, ‘‘VLSI Implementation of High Speed DSP algorithms using Vedic Mathematics’’, International Journal of Computer Communication and Information System, Vol.2. pp 119-122 Jul –Dec 2010.
- Parth Mehta, DhanashriGawelli, “Conventional Versus Vedic Mathematical method for Hardware Implementation of a multiplier”, International Conference on emerging trends in Engineering and Technology, pp 640-642, 2009.
- M.Ramalatha, K.DeenaDayalan, S. Deborah Priya, P.Dharani, ‘‘High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques”, ACTEA IEEE ZoukMosbeh, Lebanon, pp 600-603 July 15-17, 2009.
- Ramalatha M, Deena Dayalan, Thanushkodi K, Dharani P,‘‘A Novel Time and Energy Efficient Cubing Circuit using Vedic Mathematics for Finite Field Arithmetic”, International Conference on Advances in Recent Technologies in Communication and Computing , pp 873-875, 2009.
- Harpreet Singh Dhillon and AbhijitMitra, ‘‘A Reduced Bit Multiplication Algorithm for Digital Arithmetic’s”, International Journal of Computational and Mathematical Sciences Spring, 2008.
- Anthonyo Brien, Richard Conway, ‘‘Lifting Scheme Discrete Wavelet Transform using Vertical and Crosswise Multipliers”, ISSC, Galway June 18-19 pp 331-336, 2008.
- Honey DurgaTiwari, GanzorigGankhuyag, Chan Mo Kim, Yong Beom Cho, ‘‘Multiplier design based on ancient Indian Vedic Mathematics,” International SoC Design Conference, pp 65-68, 2008.
- Hanumantharaju M.C, Jayalaxmi H, Renuka R. K, Ravishankar M,‘‘A High Speed Block Convolution using Ancient Indian Vedic Mathematics,” International Conference on Computational Intelligence and Multimedia Application , pp 169-173, 2007.
- ShamainAkhter, ‘‘VHDL Implementation of Fast NxN Multiplier based on Vedic Mathematics”, Jaypee Institute of Information Technology University, Noida, 201307op, India, IEEE 2007.
- Dr. K. S.Gurumurthy, M. S. Prahalad, ‘‘Fast and Power Efficient 16x16 Array of Multiplier Using Vedic Multiplication”, International Conference on Computational Intelligence and Multimedia Application, 2006.
- Abhijeet Kumar, Dilip Kumar Siddhi, “Hardware Implementation of 16*16 bit Multiplier and Square using Vedic Mathematics”, Design Engineer, CDAC, Mohali.
Index Terms
Keywords