CFP last date
20 March 2024
Call for Paper
April Edition
IJCA solicits high quality original research papers for the upcoming April edition of the journal. The last date of research paper submission is 20 March 2024

Submit your paper
Know more
Reseach Article

C-slow Technique vs. Multiprocessor in designing low Area Customized Instruction set Processor for Embedded Applications

by Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 36 - Number 7
Year of Publication: 2011
Authors: Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz

Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz . C-slow Technique vs. Multiprocessor in designing low Area Customized Instruction set Processor for Embedded Applications. International Journal of Computer Applications. 36, 7 ( December 2011), 30-36. DOI=10.5120/4504-6362

@article{ 10.5120/4504-6362,
author = { Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz },
title = { C-slow Technique vs. Multiprocessor in designing low Area Customized Instruction set Processor for Embedded Applications },
journal = { International Journal of Computer Applications },
issue_date = { December 2011 },
volume = { 36 },
number = { 7 },
month = { December },
year = { 2011 },
issn = { 0975-8887 },
pages = { 30-36 },
numpages = {9},
url = { },
doi = { 10.5120/4504-6362 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T20:22:33.337442+05:30
%A Muhammad Adeel Akram
%A Aamir Khan
%A Muhammad Masood Sarfaraz
%T C-slow Technique vs. Multiprocessor in designing low Area Customized Instruction set Processor for Embedded Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 36
%N 7
%P 30-36
%D 2011
%I Foundation of Computer Science (FCS), NY, USA

The demand for high performance embedded processors, for consumer electronics, is rapidly increasing for the past few years. Many of these embedded processors depend upon custom built Instruction Ser Architecture (ISA) such as game processor (GPU), multimedia processors, DSP processors etc. Primary requirement for consumer electronic industry is low cost with high performance and low power consumption. A lot of research has been evolved to enhance the performance of embedded processors through parallel computing. But some of them focus superscalar processors i.e. single processors with more resources like Instruction Level Parallelism (ILP) which includes Very Long Instruction Word (VLIW) architecture, custom instruction set extensible processor architecture and others require more number of processing units on a single chip like Thread Level Parallelism (TLP) that includes Simultaneous Multithreading (SMT), Chip Multithreading (CMT) and Chip Multiprocessing (CMP). In this paper, we present a new technique, named C-slow, to enhance performance for embedded processors for consumer electronics by exploiting multithreading technique in single core processors. Without resulting into the complexity of micro controlling with Real Time Operating system (RTOS), C-slowed processor can execute multiple threads in parallel using single datapath of Instruction Set processing element. This technique takes low area & approach complexity of general purpose processor running RTOS.

  1. John Goodacre, Andrew N. Sloss, Parallelism and the ARM Instruction Set Architecture, IEEE Published by the IEEE Computer Society, 2005
  2. W. Knight, “Two Heads Are Better Than One”, IEEE Review, September 2005
  3. D. Pham et al. The Design and Implementation of a First Generation CELL Processor. In Proceeding of the IEEE International Solid-State Circuits Conference, 2005.
  4. J. Cornish. Balanced Energy Optimization. In International Symposium on Low Power Electronics and Design, 2004
  5. A. Suga et al. FR-V Single-Chip Multicore Processor: FR1000. Fujitsu Sci Tech J, 42(2):190–199, 2006.
  6. Schlett M., “Trends in embedded-microprocessor design”, IEEE Computer, pp. 44–49, Aug. 1998.
  7. “An Infrastructure for Designing Custom Embedded Counterflow Pipelines” Proceedings of the 33rd Hawaii International Conference on System Sciences – 2000
  8. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous Multithreading: Maximizing On-chip Parallelism. Proceedings of the 22nd International Symposium on Computer Architecture, pp. 206-218, June 1995.
  9. “Simultaneous Multithreading: a Platform for Next Generation Processors” Paulo Alexandre Vilarinho Assis IEEE MICRO September/October 1997
  10. Instruction Level Parallelism through Microthreading—A Scalable Approach to Chip Multiprocessors. The Computer Journal 2006 49(2). British Computer Society
  11. Instruction-Level Parallel Processing: History, Overview and Perspective The Journal of Supercomputing, Volume 7, No.1, January, 1993
  12. D.W. Wall, ”Limits of Instruction-Level Parallelism,” Pruc. Fourth Int‘l Con5 Architectural Support for Programming Languages and Operating Systems, pp. 176-188, Apr. 1991.
  13. M. Johnson, “Super-scalar Processor Design,” Technical Report No. CSL-TR-89-383, Stanford Univ., June 1989.
  14. K. Murakami, N. Irie, M. Kuga, and S. Tomita,”SIMP (Single Instruction Stream/Multiple Instruction Pipelining): A Novel High-speed Single-Processor Architecture,” Proc. 16th Ann. Int’l Symp. Computer Architecture, pp. 78-85, May 1989.
  15. EXPLOITING INSTRUCTIONAND DATA-LEVEL PARALLELISM. Roger Espasa Mateo Valero Polytechnic University of Catalunya-Barcelona IEEE Micro September/October 1997
  16. The Superthreaded Processor Architecture Jenn-Yuan Tsai, Member, IEEE, Jian Huang, Student Member, IEEE, Christoffer Amlo, David J. Lilja, Senior Member, IEEE, and Pen-Chung Yew, Fellow, IEEE, IEEE TRANSACTIONS ON COMPUTERS, VOL. 48, NO. 9, SEPTEMBER 1999
  17. M.S. Schlansker and B.R. Rau, EPIC: An Architecture for Instruction-Level Parallel Processors, HPL Tech. Report HPL-1999-111, Hewlett-Packard Laboratories, Jan. 2000.
  18. IA-64 Application Developer’s Architecture Guide, Intel Corp., 1999.
  19. M. S. Schlansker and B. R. R. Cover, “EPIC: Explicitly parallel instruction computing,” Computer, vol. 33, no. 2, pp. 37–45, Feb. 2000.
  20. H. Sharangpani and K. Arora, “Itanium processor microarchitecture,” IEEE Micro, vol. 20, pp. 24–43, Sept./Oct. 2000.
  21. SMTA: next-generation high-performance multi-threaded processor. J.-F. Tu and L.-H. Wang IEEE Proc.-Comput. Digit. Tech., Vol. 149, No. 5, September 2002
  22. K. Sankaralingam et al. , “Exploiting ILP TLP, and DLP with the Polymorphous TRIPS Architecture,” Proc. 30th Int’l Symp. Computer Architecture (ISCA 03), ACM Press, 2003, pp. 422-433.
  23. DESIGN SPACE EXPLORATION FOR REAL-TIME EMBEDDED STREAM PROCESSORS Joseph R. Cavallaro Scott Rixner Rice University Sridhar Rajagopal WiQuest Communications IEEE MICRO JULY–AUGUST 2004
  24. Area and System Clock Effects on SMT/CMP Throughput James Burns and Jean-Luc Gaudiot, Fellow, IEEE, IEEE TRANSACTIONS ON COMPUTERS, VOL. 54, NO. 2, FEBRUARY 2005
  25. R. Bahr, S. Ciavaglia, B. Flahive, M. Kline, P. Mageau and D. Nickel. The DNl0000TX: a new high-performance PRISM processor. Proc. COMPCON '91 (1991). 7G. Blanck and S. Krueger. The SuperSPARCrM microprocessor. Proc. COMPCON '92 (1992), 136-141
  26. 2M. Johnson. Superscalar Microprocessor Design. (Prentice-Hall, Englewood Cliffs, New Jersey, 1991).
  27. N. P. Jouppi. The nonuniform distribution of instruction-level and machine parallelism and its effect on performance. IEEE Transactions on Computers C-38, 12 (December 1989), 1645-1658
  28. C. Leiserson, F. Rose, and J. Saxe, “Optimizing synchronous circuitry by retiming,” Proceedings of the 3rd Caltech Conference On VLSI, pp. 87-116, March 1983.
  29. N. Weaver, Y. Markovskiy, Y. Patel and J. Wawrzynek, “Post placement c-slow retiming for the Xilinx Virtex FPGA,” Proceedings of the 11th ACM Symposium of Field Programmable Gate Arrays, Feb. 2003, pp. 185-194.
  30. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, B. Smith. The Tera computer system. Proceedings of the 1990 International Conference on Supercomputing, 1990.
Index Terms

Computer Science
Information Sciences


Instruction Set Architecture (ISA) Instruction Level Parallelism (ILP) Very Long Instruction Word (VLIW) Thread Level Parallelism (TLP) Simultaneous Multithreading (SMT) Chip Multithreading (CMT) Chip Multiprocessing (CMP)