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Minimization of Switching Losses for Diode Clamped Multilevel Inverter
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 44 - Number 11 |
| Year of Publication: 2012 |
| Authors: R. Pon Perumal, W. Razia Sultana, Sarat Kumar Sahoo |
10.5120/6305-8625
|
R. Pon Perumal, W. Razia Sultana, Sarat Kumar Sahoo . Minimization of Switching Losses for Diode Clamped Multilevel Inverter. International Journal of Computer Applications. 44, 11 ( April 2012), 6-11. DOI=10.5120/6305-8625
Abstract
Multilevel inverters are emerging as a most promising alternative for reducing the harmonics and to achieve high-voltage, high-power capability but switching losses are increased because of increased device count. Many modulation techniques like soft switching techniques, space vector-based PWM techniques or sinusoidal PWM-based techniques were employed to reduce the switching losses. In this paper, a carrier-based closed-loop PWM control technique has been proposed based on insertion of 'no switching' zone within each positive and negative half cycle of fundamental wave to reduce the switching losses. This method effectively reduces the switching losses of three-level inverter as it does not require any complex mathematical expressions involved in space vector based technique. Moreover, THD is found within 5% for a switching frequency of 5 kHz with proposed technique over conventional SPWM technique. Simulation results are presented to validate the proposed technique. Comparisons are made between switching losses of conventional and proposed control technique of three level diode clamped inverter.
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