The week's pick
Reseach Article
A High Speed Parallel Counter Architecture and its Implementation in Programmable Square Finder cum Frequency Divider Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 46 - Number 12 |
| Year of Publication: 2012 |
| Authors: Pramod.p |
10.5120/6961-9457
|
Pramod.p . A High Speed Parallel Counter Architecture and its Implementation in Programmable Square Finder cum Frequency Divider Circuit. International Journal of Computer Applications. 46, 12 ( May 2012), 22-27. DOI=10.5120/6961-9457
Abstract
An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circuit outputs a sequence of states and the modulus is determined by the external frequency select input. The Square finder circuit finds the square of the given number by repetitively adding the number that much times. The counter consists of two main sections- the counting section and the state Anticipation Module. The 8-bit square finder cum frequency divider employing existing counter architecture [5] consumes a total transistor count of 1206 whereas the same using proposed counter architecture consumes only 1038. The worst case delay of the proposed programmable square finder cum frequency divider architecture employing the existing and proposed counter architecture was found to be 21. 829ns and 20. 686 respectively and the Power dissipation at 250 MHz was found to be 6. 35 mW and 5. 77mW respectively.
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