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Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application

by B. Sathiyabama, S. Malarkkan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 46 - Number 16
Year of Publication: 2012
Authors: B. Sathiyabama, S. Malarkkan
10.5120/6993-9472

B. Sathiyabama, S. Malarkkan . Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application. International Journal of Computer Applications. 46, 16 ( May 2012), 16-20. DOI=10.5120/6993-9472

@article{ 10.5120/6993-9472,
author = { B. Sathiyabama, S. Malarkkan },
title = { Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application },
journal = { International Journal of Computer Applications },
issue_date = { May 2012 },
volume = { 46 },
number = { 16 },
month = { May },
year = { 2012 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume46/number16/6993-9472/ },
doi = { 10.5120/6993-9472 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:39:54.427981+05:30
%A B. Sathiyabama
%A S. Malarkkan
%T Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application
%J International Journal of Computer Applications
%@ 0975-8887
%V 46
%N 16
%P 16-20
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multipliers and adders are the most significant part of all data path circuits in the microprocessor and digital signal processor. The power and speed of the multiplier and adder affects the entire performance of the system. In this paper, low power multiplier using Hybrid adder is proposed. Also it presents the analysis of three modified multipliers: Braun array multiplier, Baugh Wooley array multiplier, and CSA Multiplier with optimized adders. The multipliers are designed with optimized Hybrid and other adders using transistor sizing technique. The performance of power and delay of the multipliers are analyzed with optimization. All circuits are implemented in HSPICE BSIM model at 90nm deep submicron technology

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Index Terms

Computer Science
Information Sciences

Keywords

Dynamic Power Cmosfa Lpfa Tgfa Tgdcfa Sfa Cpl

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