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Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 46 - Number 16
Year of Publication: 2012
Authors:
B. Sathiyabama
S. Malarkkan
10.5120/6993-9472

B Sathiyabama and S Malarkkan. Article: Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application. International Journal of Computer Applications 46(16):16-20, May 2012. Full text available. BibTeX

@article{key:article,
	author = {B. Sathiyabama and S. Malarkkan},
	title = {Article: Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {46},
	number = {16},
	pages = {16-20},
	month = {May},
	note = {Full text available}
}

Abstract

Multipliers and adders are the most significant part of all data path circuits in the microprocessor and digital signal processor. The power and speed of the multiplier and adder affects the entire performance of the system. In this paper, low power multiplier using Hybrid adder is proposed. Also it presents the analysis of three modified multipliers: Braun array multiplier, Baugh Wooley array multiplier, and CSA Multiplier with optimized adders. The multipliers are designed with optimized Hybrid and other adders using transistor sizing technique. The performance of power and delay of the multipliers are analyzed with optimization. All circuits are implemented in HSPICE BSIM model at 90nm deep submicron technology

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