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Performance Analysis of Floating Point Adder using VHDL on Reconfigurable Hardware

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 46 - Number 9
Year of Publication: 2012
Authors:
Karan Gumber
Sharmelee Thangjam
10.5120/6934-9205

Karan Gumber and Sharmelee Thangjam. Article: Performance Analysis of Floating Point Adder using VHDL on Reconfigurable Hardware. International Journal of Computer Applications 46(9):1-5, May 2012. Full text available. BibTeX

@article{key:article,
	author = {Karan Gumber and Sharmelee Thangjam},
	title = {Article: Performance Analysis of Floating Point Adder using VHDL on Reconfigurable Hardware},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {46},
	number = {9},
	pages = {1-5},
	month = {May},
	note = {Full text available}
}

Abstract

Floating point addition is more difficult than multiplication because alignment of mantissa is required before mantissa addition. The main objective of implementation of floating point adder on reconfigurable hardware i. e. on Virtex is to utilize less chip area with less combinational delay and faster speed. Less combinational delay means less latency i. e. less time is required to appear an output after the input response is applied and if there is less latency then there will be the faster speed and lesser the clock period. Implementation of floating point adder on Virtex 4 produces a least combinational delay of 24. 201nsec consuming 4% of chip area while implementing same on Spartan 2 produces the greatest combinational delay of 79. 594nsec consuming 92% of chip area. Less chip area means less number of slices is used in reconfigurable hardware i. e. on FPGAs.

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