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Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression

by M. Nagabushanam, S. Ramachandran
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 51 - Number 6
Year of Publication: 2012
Authors: M. Nagabushanam, S. Ramachandran
10.5120/8049-1383

M. Nagabushanam, S. Ramachandran . Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression. International Journal of Computer Applications. 51, 6 ( August 2012), 35-41. DOI=10.5120/8049-1383

@article{ 10.5120/8049-1383,
author = { M. Nagabushanam, S. Ramachandran },
title = { Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression },
journal = { International Journal of Computer Applications },
issue_date = { August 2012 },
volume = { 51 },
number = { 6 },
month = { August },
year = { 2012 },
issn = { 0975-8887 },
pages = { 35-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume51/number6/8049-1383/ },
doi = { 10.5120/8049-1383 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:50:14.934168+05:30
%A M. Nagabushanam
%A S. Ramachandran
%T Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression
%J International Journal of Computer Applications
%@ 0975-8887
%V 51
%N 6
%P 35-41
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using 130nm Technology. 2D DWT architecture based on lifting scheme architecture uses multipliers and adders, thus consuming power. This paper addresses power reduction in multiplier by proposing a modified algorithm for BZFAD multiplier. The proposed BZFAD multiplier is 65% faster and occupies 44% less area compared with the generic multipliers. The DWT architecture designed based on modified BZFAD multiplier achieves 35% less power reduction and operates at frequency of 200MHz with latency of 1536 clock cycles for 512x512 images. The 3D-DWT architecture is designed for 8x8x8 video frame, based on fast lifting scheme approach using (9, 7) wavelet filter. Using 9/7 filter for DWT computation reduces the hardware complexity, memory accesses and achieves minimum error in reconstruction of images. The proposed architecture systematically combines hardware optimization techniques to develop a flexible DWT architecture that has high performance and is suitable for portable, high speed, low power applications. 3D-DWT architecture has been implemented on Virtex-5 FPGA with utilization of 1,152 out of 19,200(5%) slice registers and the frequency of operation is 256. 20MHz. The developed DWT can be used as an IP for VLSI implementation.

References
  1. Tze-Yun Sung, Hsi-Chin Hsin Yaw-Shih Shieh and Chun-Wang Yu, "Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters", Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies, December 2006.
  2. Abdullah AL Muhit, Md. Shabiul Islam and Masuri Othman, "VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression", 2nd International Conference on Autonomous Robots and Agents, 13-15 December 2004.
  3. Motra A. S. Bora P. K. and Chakrabarti I. "An efficient hardware implementation of DWT and IDWT", Conference on Convergent Technologies for Asia-Pacific Region, 15-17 October 2003.
  4. Yun-Nan Chang and Yan-Sheng Li, "Design of highly efficient VLSI architectures for 2-D DWT and 2-D IDWT", IEEE Workshop on Signal Processing Systems, 26-28 September 2001.
  5. Keshab K. Parhi and Takao Nishitani, "VLSI architectures for discrete wavelet transforms", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 2, pp. 191-202, June 1993.
  6. David S. Taubman, Michael W. Marcellin, "JPEG 2000 – Image compression, fundamentals, standards and practice", Kluwer academic publishers, Second Edition, 2002.
  7. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto and Antonino Tumeo, "Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA", Embedded Computer Systems: Architectures, Modeling and Simulation, 2006. IC-SAMOS 2006, July 2006, pp. 107 - 114.
  8. Mel Tsai, BDTI, "Designing Low-Power Signal Processing Systems", http://www. dspdesignline. com/showArticle. jhtml?articleID=187002923.
  9. Tze-Yun, "Low-power and high-performance 2-D DWT and IDWT architectures based on 4-tap Daubechies filters", Proceedings of the 7th WSEAS International Conference on Multimedia Systems and Signal Processing, Hangzhou, China, pp. 50-55, 2007.
  10. S. Baloch, I. Ahmed, T. Arslan, A. Stoica, "Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications, "International Conference on Field Programmable Logic and Applications", pp. 618-621, International Conference on Field Programmable Logic and Applications, 2005.
  11. Anirban Das, Anindya Hazra, and Swapna Banerjee,"An Efficient Architecture for 3-D Discrete Wavelet Transform" IEEE Transactions on circuits and systems for video technology, vol. 20, no. 2, February 2010.
  12. Chin-Fa Hsieh , Tsung-Han Tsai , Neng-Jye Hsu , and Chih-Hung Lai, " A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes" Department. of Electronics Engineering, China Institute of Technology, Taipei, Taiwan and Department. of Electrical Engineering, National Central University, Chung-Li, Taiwan, IEEE Trans 2004.
  13. Kuan-Hung Chen and Yuan-Sun Chu, "A Low-Power Multiplier with the Spurious Power Suppression Technique," IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 15, no. 7, July 2007, pp. 846-850.
  14. Kishore Andra, Chaitali Chakrabarti and Tinku Acharya, "A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform" IEEE Transaction on signal processing , VOL. 50, NO. 4, pp. 966-977, April 2002.
  15. Movva S and Srinivasan S "A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI Implementation" VLSI Design, 2003. Proceedings. 16th International Conference On4-8,Jan2003 Page(s): 202 – 207. Washington,DC,USA
  16. Dusan Suvakovic, C. Andre, Salama "A Pipelined Multiply-Accumulate Unit Design for Energy Recovery DSP Systems" IEEE International Symposium on Circuits and Systems, May 28-31, 2000.
  17. Jung- Yup Kang, Jean-Luc Gaudiot, "A Simple High-Speed Multiplier Design" IEEE Transactions on computers, Vol 55, No 10, October 2006, pp 1253 – 1258.
  18. Zhijun Huang, Milos D. Ercegovac, "High-performance Low-power Left-to-Right Array Multiplier Design" IEEE Transactions on computers, Vol 54, No. 3, Mar 2005, pp 272 – 283.
  19. C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. computers, vol 13, no. 2, pp 14 – 17, 1964.
  20. Vojin G. Oklobzija, Bart R. Zaydel, Hoang Q. Dao, Sanu Mathew and Ram Krishnamurthy, "Comparison of high-performance VLSI adders in the energy-delay space", IEEE Trans. VLSI Systems, vol. 13, no. 6, pp. 754-758, June 2005.
  21. J-Y Kang and J-L Gaudiot, "A Fast and Well structured Multiplier," EUROMICRO Symp. Digital System Design, pp. 508 – 515, Aug 2004.
  22. Nagabushanam,M. , Cyril prasanna Raj, and Ramachandran,S. 'ModifiedVLSI implementation of DA-DWT for image compression', International Journal of Signal and Imaging Systems Engineering, (to be published by inderscience)Vol. x, No. x, pp. xxx–xxx.
  23. Nagabushanam,M. , Cyril prasanna Raj, and Ramachandran,S. (2009),'Design and implementation of parallel and pipelined Distributive arithmetic based discrete wavelet transform IP core', EJSR International Journal, Vol. 35. No. 3, pp. 379–392.
  24. Nagabushanam, M. , Cyril Prasanna Raj, and Ramachandran, S. (2011), 'Design and FPGA implementation of Modified Distributive arithmetic based DWT-IDWT processor for image compression', International Conference on Communication and Signal Processing, February, NIT, Calicut, India, p. 69.
  25. Nagabushanam, M. and Ramachandran, S. 'Fast Implementation of Lifting based DWT Architecture for Image Compression', Global Journal of Computer Science and Technology (F), Volume – XII, Issue XI, Version I, p. 23-29. , June 2012.
  26. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture, IEEE Transactions on Very large Scale Integration (VLSI)systems, VOL. 17, no. 2, Feb2009.
Index Terms

Computer Science
Information Sciences

Keywords

DWT Image compression BZFAD multiplier FPGA Lifting scheme

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